cda4210_lisp_coproc, branch HEADA primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK)06b6b116934cc8341676f52f5f6040a038020c322025-12-10T21:35:42Z2025-12-10T21:39:36Zmigrate from electric vlsi to librelane/sky130 flowvingit@vineetk.netcommit 06b6b116934cc8341676f52f5f6040a038020c32
parent 36f4ec74c5d1247362bed901dbaf0a36970b4cd0
Author: vin <git@vineetk.net>
Date: Wed, 10 Dec 2025 16:35:42 -0500
migrate from electric vlsi to librelane/sky130 flow
this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).
this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.
36f4ec74c5d1247362bed901dbaf0a36970b4cd02025-12-09T03:19:25Z2025-12-09T03:19:40Zfinal changes from electric before moving to librelanevingit@vineetk.netcommit 36f4ec74c5d1247362bed901dbaf0a36970b4cd0
parent 95997aac1be995dce6bc6fdb01a2880242700e8f
Author: vin <git@vineetk.net>
Date: Mon, 8 Dec 2025 22:19:25 -0500
final changes from electric before moving to librelane
This is the commit used for my class's final report. Now I'm free to
use whatever tool I want. Cadence/Synopsys seems to be much more
automated compared to Electric, and LibreLane (previously OpenLane)
seems to be more closely resemble that.
95997aac1be995dce6bc6fdb01a2880242700e8f2025-12-01T22:13:00Z2025-12-01T22:13:00Zfix mux16 layout input orderingvingit@vineetk.netcommit 95997aac1be995dce6bc6fdb01a2880242700e8f
parent e32c69a3677cf346c4e35ebf15450c6d38190f58
Author: vin <git@vineetk.net>
Date: Mon, 1 Dec 2025 17:13:00 -0500
fix mux16 layout input ordering
e32c69a3677cf346c4e35ebf15450c6d38190f582025-12-01T21:13:41Z2025-12-01T21:13:41Zsome more changesvingit@vineetk.netcommit e32c69a3677cf346c4e35ebf15450c6d38190f58
parent 613ae59a5258f1adbe0ce1082f7cccacceed3fbd
Author: vin <git@vineetk.net>
Date: Mon, 1 Dec 2025 16:13:41 -0500
some more changes
613ae59a5258f1adbe0ce1082f7cccacceed3fbd2025-11-30T07:38:59Z2025-11-30T07:38:59Zadd more gates and make some changes to layouts for easier tilingvingit@vineetk.netcommit 613ae59a5258f1adbe0ce1082f7cccacceed3fbd
parent e63bae1212549b998d610e7701400ee59b404944
Author: vin <git@vineetk.net>
Date: Sun, 30 Nov 2025 02:38:59 -0500
add more gates and make some changes to layouts for easier tiling
e63bae1212549b998d610e7701400ee59b4049442025-11-29T07:08:32Z2025-11-29T07:08:32Zadd 6-bit rca and 8-bit equivalentvingit@vineetk.netcommit e63bae1212549b998d610e7701400ee59b404944
parent e89d2328c9aac46de6fbc420be9a8b617ab3188a
Author: vin <git@vineetk.net>
Date: Sat, 29 Nov 2025 02:08:32 -0500
add 6-bit rca and 8-bit equivalent
e89d2328c9aac46de6fbc420be9a8b617ab3188a2025-11-28T12:05:38Z2025-11-28T12:05:38Zfinish making primitive cells (passes DRC+ERC+LVS)vingit@vineetk.netcommit e89d2328c9aac46de6fbc420be9a8b617ab3188a
parent 1c7666facade946e9fd58ce779789e50994ec4a2
Author: vin <git@vineetk.net>
Date: Fri, 28 Nov 2025 07:05:38 -0500
finish making primitive cells (passes DRC+ERC+LVS)
1c7666facade946e9fd58ce779789e50994ec4a22025-11-20T17:01:31Z2025-11-20T17:01:31Zadd more comprehensive test benchvingit@vineetk.netcommit 1c7666facade946e9fd58ce779789e50994ec4a2
parent 46303e07e9bda309cb451aa824680db9bdd19fe8
Author: vin <git@vineetk.net>
Date: Thu, 20 Nov 2025 12:01:31 -0500
add more comprehensive test bench
46303e07e9bda309cb451aa824680db9bdd19fe82025-11-20T16:27:13Z2025-11-20T16:27:13Zfix lint errors from icarus-verilog and verilatorvingit@vineetk.netcommit 46303e07e9bda309cb451aa824680db9bdd19fe8
parent 8e17e8bc9d84fbaa5c06bf549faf754f087c8ce6
Author: vin <git@vineetk.net>
Date: Thu, 20 Nov 2025 11:27:13 -0500
fix lint errors from icarus-verilog and verilator
8e17e8bc9d84fbaa5c06bf549faf754f087c8ce62025-11-20T16:16:32Z2025-11-20T16:16:32Zfix rtl, now tests all passvingit@vineetk.netcommit 8e17e8bc9d84fbaa5c06bf549faf754f087c8ce6
parent 4dd69d2913152d80af58d7d68fd195c031180606
Author: vin <git@vineetk.net>
Date: Thu, 20 Nov 2025 11:16:32 -0500
fix rtl, now tests all pass
need to go through the sv files again and also run a linter
4dd69d2913152d80af58d7d68fd195c0311806062025-11-20T16:01:48Z2025-11-20T16:01:48Zinitial golden rtlvingit@vineetk.netcommit 4dd69d2913152d80af58d7d68fd195c031180606
Author: vin <git@vineetk.net>
Date: Thu, 20 Nov 2025 11:01:48 -0500
initial golden rtl