cda4210_lisp_coproc/Makefile, branch master A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) migrate from electric vlsi to librelane/sky130 flow 2025-12-10T21:39:36+00:00 vin git@vineetk.net 2025-12-10T21:35:42+00:00 06b6b116934cc8341676f52f5f6040a038020c32 this is quite a major shift. moves the project from a manual, full-custom layout workflow to a more modern automated flow and a more modern process (130nm vs 350nm). also improved the testbench. migration also resolves previous manual routing-caused errors (like the CONS logic bug and difficulty in implementing TG logic). this nearly halved the transistor count from 15k to 8k and reduced area size by 300x. 
this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).

this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.