cda4210_lisp_coproc/rtl, branch master A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) migrate from electric vlsi to librelane/sky130 flow 2025-12-10T21:39:36+00:00 vin git@vineetk.net 2025-12-10T21:35:42+00:00 06b6b116934cc8341676f52f5f6040a038020c32 this is quite a major shift. moves the project from a manual, full-custom layout workflow to a more modern automated flow and a more modern process (130nm vs 350nm). also improved the testbench. migration also resolves previous manual routing-caused errors (like the CONS logic bug and difficulty in implementing TG logic). this nearly halved the transistor count from 15k to 8k and reduced area size by 300x. 
this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).

this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.
add more comprehensive test bench 2025-11-20T17:01:31+00:00 vin git@vineetk.net 2025-11-20T17:01:31+00:00 1c7666facade946e9fd58ce779789e50994ec4a2 






fix lint errors from icarus-verilog and verilator
2025-11-20T16:27:13+00:00

vin
git@vineetk.net

2025-11-20T16:27:13+00:00

46303e07e9bda309cb451aa824680db9bdd19fe8












fix rtl, now tests all pass
2025-11-20T16:16:32+00:00

vin
git@vineetk.net

2025-11-20T16:16:32+00:00

8e17e8bc9d84fbaa5c06bf549faf754f087c8ce6

need to go through the sv files again and also run a linter





need to go through the sv files again and also run a linter







initial golden rtl
2025-11-20T16:01:48+00:00

vin
git@vineetk.net

2025-11-20T16:01:48+00:00

4dd69d2913152d80af58d7d68fd195c031180606