cda4210_lisp_coproc/vlsi/datapath.jelib, branch master A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) final changes from electric before moving to librelane 2025-12-09T03:19:40+00:00 vin git@vineetk.net 2025-12-09T03:19:25+00:00 36f4ec74c5d1247362bed901dbaf0a36970b4cd0 This is the commit used for my class's final report. Now I'm free to use whatever tool I want. Cadence/Synopsys seems to be much more automated compared to Electric, and LibreLane (previously OpenLane) seems to be more closely resemble that. 
This is the commit used for my class's final report. Now I'm free to
use whatever tool I want. Cadence/Synopsys seems to be much more
automated compared to Electric, and LibreLane (previously OpenLane)
seems to be more closely resemble that.
add more gates and make some changes to layouts for easier tiling 2025-11-30T07:38:59+00:00 vin git@vineetk.net 2025-11-30T07:38:59+00:00 613ae59a5258f1adbe0ce1082f7cccacceed3fbd 






add 6-bit rca and 8-bit equivalent
2025-11-29T07:08:32+00:00

vin
git@vineetk.net

2025-11-29T07:08:32+00:00

e63bae1212549b998d610e7701400ee59b404944