| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2025-12-01 | fix mux16 layout input ordering | vin | 1 | -76/+77 |
| 2025-12-01 | some more changes | vin | 1 | -113/+1230 |
| 2025-11-30 | add more gates and make some changes to layouts for easier tiling | vin | 3 | -410/+2158 |
| 2025-11-29 | add 6-bit rca and 8-bit equivalent | vin | 2 | -84/+829 |
| 2025-11-28 | finish making primitive cells (passes DRC+ERC+LVS) | vin | 1 | -0/+1189 |
| 2025-11-20 | add more comprehensive test bench | vin | 1 | -94/+254 |
| 2025-11-20 | fix lint errors from icarus-verilog and verilator | vin | 1 | -5/+10 |
| 2025-11-20 | fix rtl, now tests all pass | vin | 3 | -317/+240 |
| 2025-11-20 | initial golden rtl | vin | 3 | -0/+442 |
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index : cda4210_lisp_coproc | |
| A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) | Vineet K |
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