# ==============================================================================
# CONFIGURATION
# ==============================================================================
PROJECT_NAME = lisp_coproc
CONFIG_FILE  = config.json

# Tool Paths
LIBRELANE    = librelane
VERILATOR    = verilator

# PDK Paths (Standard Volare location)
PDK_ROOT     ?= $(HOME)/.ciel/ciel/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/
PDK          = sky130A
LIB_VERILOG  = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
PRIM_VERILOG = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v

# Simulation Flags
VERILATOR_FLAGS = --binary -j 0 --timing --trace --top-module tb_$(PROJECT_NAME) \
                  -Wno-fatal -Wno-style -Wno-lint

# ==============================================================================
# TARGETS
# ==============================================================================
.PHONY: all rtl harden gls clean

# 1. Default: Run the full pipeline (RTL -> GDS -> Check)
all: rtl harden gls

# 2. RTL Verification: Runs your Golden SystemVerilog Testbench
rtl:
	@echo "\n=== [1/3] Running RTL Verification ==="
	$(VERILATOR) $(VERILATOR_FLAGS) \
		-DGL_SIM=0 \
		rtl/tb_$(PROJECT_NAME).sv rtl/$(PROJECT_NAME).sv
	./obj_dir/Vtb_$(PROJECT_NAME)
	@echo ">>> RTL Verification Passed <<<"

# 3. Hardening: Runs LibreLane (Synthesis, Place & Route)
# Note: Uses --run-tag to create a predictable folder name for the GLS step
harden:
	@echo "\n=== [2/3] Running LibreLane Hardening ==="
	$(LIBRELANE) --flow Classic \
		--run-tag automated_run \
		--overwrite \
		$(CONFIG_FILE)
	@echo ">>> Hardening Complete <<<"

# 4. Gate-Level Simulation (GLS): Verifies the final GDSII netlist
# Finds the netlist generated by the 'harden' step
GL_NETLIST = runs/automated_run/final/nl/$(PROJECT_NAME).nl.v

gls:
	@echo "\n=== [3/3] Running Gate-Level Simulation (GLS) ==="
	$(VERILATOR) $(VERILATOR_FLAGS) \
		-DGL_SIM=1 -DFUNCTIONAL -DUNIT_DELAY=\#1 \
		-I$(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog \
		rtl/tb_$(PROJECT_NAME).sv \
		$(GL_NETLIST) \
		$(LIB_VERILOG) $(PRIM_VERILOG)
	./obj_dir/Vtb_$(PROJECT_NAME)
	@echo ">>> GLS Verification Passed <<<"

# Clean up build artifacts
clean:
	rm -rf obj_dir runs/automated_run $(PROJECT_NAME).vcd