eel3792c_rv32i/riscvsingle.sv, branch masterRV32I implementation on a DE10-Lite FPGA for the EEL3792C course.increase rom to 128 from 642025-04-17T20:38:53+00:00vingit@vineetk.net2025-04-17T20:38:53+00:006c5b90cf4ac5a9e582c95a6c936d67e0c38d811d
increase RAM size to 0xff2025-04-17T20:14:48+00:00vingit@vineetk.net2025-04-17T20:14:41+00:0092d16b841168f044536636179ad4a4364f5ba29a
add blt and bge2025-03-25T20:31:35+00:00vingit@vineetk.net2025-03-25T20:31:11+00:00398f047bac2b89026dcb09ce21b4683ff49d4f35
refactor PCSrc assignment and add bne instruction2025-03-25T20:31:35+00:00vingit@vineetk.net2025-03-24T20:46:05+00:0070477dad47f985f68ce05668911939b0374ea364
remove db and incremental_db2025-03-24T20:23:48+00:00vingit@vineetk.net2025-03-24T19:45:40+00:005ba90a29a3b539ead01f5c252722185c0ee33b9e
add shift instructions (sll, srl, sra, and immediates)2025-03-24T20:23:47+00:00vingit@vineetk.net2025-03-20T20:30:16+00:00c5ccd5c22f22cbbc265555559c7eefd06428398b
add xor instruction and PC logging2025-03-20T20:08:09+00:00vingit@vineetk.net2025-03-20T20:06:12+00:006927c5bdc6009b2acb05a2a7d176003447340a34
use relative filepath for ROM and RAM2025-03-10T20:20:23+00:00vingit@vineetk.net2025-03-10T20:20:23+00:00c7a70e1962a7b6d8dfd524d39f42a7f31261450f