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-rw-r--r--cpu.c19
-rw-r--r--cpu.h2
-rw-r--r--opcodes.h70
3 files changed, 46 insertions, 45 deletions
diff --git a/cpu.c b/cpu.c
index 039337f..1345d8b 100644
--- a/cpu.c
+++ b/cpu.c
@@ -127,9 +127,7 @@ opcode_mem(enum addressing_mode mode)
127 val = (arg + regs.y) % 256; 127 val = (arg + regs.y) % 256;
128 break; 128 break;
129 case AM_REL: 129 case AM_REL:
130 val = arg + regs.pc; 130 val = (int8_t)arg + regs.pc;
131 if (((regs.pc + 1) & 0xFF00) != (val & 0xFF00))
132 val -= 0x0100;
133 break; 131 break;
134 case AM_IMM: 132 case AM_IMM:
135 case AM_ABS: 133 case AM_ABS:
@@ -174,6 +172,9 @@ branch(uint16_t addr, bool cond)
174 return; 172 return;
175 cycles++; 173 cycles++;
176 174
175 if (((regs.pc + 1) & 0xFF00) != (addr & 0xFF00))
176 cycles++;
177
177 regs.pc = addr; 178 regs.pc = addr;
178} 179}
179 180
@@ -277,7 +278,7 @@ BRK(uint16_t arg)
277{ 278{
278 /* TODO: push regs.pc and regs.status to stack and load IRQ vector */ 279 /* TODO: push regs.pc and regs.status to stack and load IRQ vector */
279 regs.status.brk = 1; 280 regs.status.brk = 1;
280 // exit(0); 281 exit(0);
281} 282}
282 283
283void 284void
@@ -771,11 +772,11 @@ DCP(uint16_t arg)
771 memwrite(arg, tmp); 772 memwrite(arg, tmp);
772 773
773 regs.status.carry = tmp <= regs.a; 774 regs.status.carry = tmp <= regs.a;
774 STATUS_UPDATE_NZ(tmp); 775 STATUS_UPDATE_NZ(regs.a - tmp);
775} 776}
776 777
777void 778void
778ISC(uint16_t arg) 779ISB(uint16_t arg)
779{ 780{
780 INC(arg); 781 INC(arg);
781 SBC(peek(arg)); 782 SBC(peek(arg));
@@ -807,7 +808,7 @@ void
807RLA(uint16_t arg) 808RLA(uint16_t arg)
808{ 809{
809 ROL(arg); 810 ROL(arg);
810 AND(arg); 811 AND(peek(arg));
811} 812}
812 813
813void 814void
@@ -821,14 +822,14 @@ void
821SLO(uint16_t arg) 822SLO(uint16_t arg)
822{ 823{
823 ASL(arg); 824 ASL(arg);
824 ORA(arg); 825 ORA(peek(arg));
825} 826}
826 827
827void 828void
828SRE(uint16_t arg) 829SRE(uint16_t arg)
829{ 830{
830 LSR(arg); 831 LSR(arg);
831 EOR(arg); 832 EOR(peek(arg));
832} 833}
833 834
834void 835void
diff --git a/cpu.h b/cpu.h
index 3002573..ed17432 100644
--- a/cpu.h
+++ b/cpu.h
@@ -72,7 +72,7 @@ void AXA(uint16_t arg);
72void AXS(uint16_t arg); 72void AXS(uint16_t arg);
73void DCP(uint16_t arg); 73void DCP(uint16_t arg);
74void DOP(uint16_t arg); 74void DOP(uint16_t arg);
75void ISC(uint16_t arg); 75void ISB(uint16_t arg);
76void KIL(uint16_t arg); 76void KIL(uint16_t arg);
77void LAR(uint16_t arg); 77void LAR(uint16_t arg);
78void LAX(uint16_t arg); 78void LAX(uint16_t arg);
diff --git a/opcodes.h b/opcodes.h
index 020e8f3..89d5f73 100644
--- a/opcodes.h
+++ b/opcodes.h
@@ -220,13 +220,13 @@ struct opcode opcodes[0x100] = {
220 [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, 220 [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X },
221 [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, 221 [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM },
222 [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, 222 [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X },
223 [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, 223 [0xE7] = { "ISB", ISB, 2, 5, false, true, false, true, AM_ZP },
224 [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, 224 [0xF7] = { "ISB", ISB, 2, 6, false, true, false, true, AM_ZP_X },
225 [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, 225 [0xEF] = { "ISB", ISB, 3, 6, false, true, false, true, AM_ABS },
226 [0xFF] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_X }, 226 [0xFF] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_X },
227 [0xFB] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_Y }, 227 [0xFB] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_Y },
228 [0xE3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_X }, 228 [0xE3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_X },
229 [0xF3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_Y }, 229 [0xF3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_Y },
230 [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, 230 [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
231 [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, 231 [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
232 [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, 232 [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
@@ -252,35 +252,35 @@ struct opcode opcodes[0x100] = {
252 [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, 252 [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
253 [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, 253 [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
254 [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, 254 [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
255 [0x27] = { "RLA", RLA, 2, 5, true, true, false, true, AM_ZP }, 255 [0x27] = { "RLA", RLA, 2, 5, false, true, false, true, AM_ZP },
256 [0x37] = { "RLA", RLA, 2, 6, true, true, false, true, AM_ZP_X }, 256 [0x37] = { "RLA", RLA, 2, 6, false, true, false, true, AM_ZP_X },
257 [0x2F] = { "RLA", RLA, 3, 6, true, true, false, true, AM_ABS }, 257 [0x2F] = { "RLA", RLA, 3, 6, false, true, false, true, AM_ABS },
258 [0x3F] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_X }, 258 [0x3F] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_X },
259 [0x3B] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_Y }, 259 [0x3B] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_Y },
260 [0x23] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_X }, 260 [0x23] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_X },
261 [0x33] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_Y }, 261 [0x33] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_Y },
262 [0x67] = { "RRA", RRA, 2, 5, true, true, false, true, AM_ZP }, 262 [0x67] = { "RRA", RRA, 2, 5, false, true, false, true, AM_ZP },
263 [0x77] = { "RRA", RRA, 2, 6, true, true, false, true, AM_ZP_X }, 263 [0x77] = { "RRA", RRA, 2, 6, false, true, false, true, AM_ZP_X },
264 [0x6F] = { "RRA", RRA, 3, 6, true, true, false, true, AM_ABS }, 264 [0x6F] = { "RRA", RRA, 3, 6, false, true, false, true, AM_ABS },
265 [0x7F] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_X }, 265 [0x7F] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_X },
266 [0x7B] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_Y }, 266 [0x7B] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_Y },
267 [0x63] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_X }, 267 [0x63] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_X },
268 [0x73] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_Y }, 268 [0x73] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_Y },
269 [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, 269 [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM },
270 [0x07] = { "SLO", SLO, 2, 5, true, true, false, true, AM_ZP }, 270 [0x07] = { "SLO", SLO, 2, 5, false, true, false, true, AM_ZP },
271 [0x17] = { "SLO", SLO, 2, 6, true, true, false, true, AM_ZP_X }, 271 [0x17] = { "SLO", SLO, 2, 6, false, true, false, true, AM_ZP_X },
272 [0x0F] = { "SLO", SLO, 3, 6, true, true, false, true, AM_ABS }, 272 [0x0F] = { "SLO", SLO, 3, 6, false, true, false, true, AM_ABS },
273 [0x1F] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_X }, 273 [0x1F] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_X },
274 [0x1B] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_Y }, 274 [0x1B] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_Y },
275 [0x03] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_X }, 275 [0x03] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_X },
276 [0x13] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_Y }, 276 [0x13] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_Y },
277 [0x47] = { "SRE", SRE, 2, 5, true, true, false, true, AM_ZP }, 277 [0x47] = { "SRE", SRE, 2, 5, false, true, false, true, AM_ZP },
278 [0x57] = { "SRE", SRE, 2, 6, true, true, false, true, AM_ZP_X }, 278 [0x57] = { "SRE", SRE, 2, 6, false, true, false, true, AM_ZP_X },
279 [0x4F] = { "SRE", SRE, 3, 6, true, true, false, true, AM_ABS }, 279 [0x4F] = { "SRE", SRE, 3, 6, false, true, false, true, AM_ABS },
280 [0x5F] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_X }, 280 [0x5F] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_X },
281 [0x5B] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_Y }, 281 [0x5B] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_Y },
282 [0x43] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_X }, 282 [0x43] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_X },
283 [0x53] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_Y }, 283 [0x53] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_Y },
284 [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y }, 284 [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y },
285 [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X }, 285 [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X },
286 [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, 286 [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS },