1 files changed, 29 insertions, 0 deletions

diff --git a/guix-science/packages/electronics.scm b/guix-science/packages/electronics.scm
index 6a4b3b3..3e5c6cf 100644
--- a/guix-science/packages/electronics.scm
+++ b/guix-science/packages/electronics.scm
@@ -216,6 +216,35 @@ used as an experimental synthesizer backend.")
        "This plugin provides a shared library module for Yosys to implement logical synthesis of VHDL designs.")
       (license license:gpl3+))))
 
+(define-public python-cocotb
+  (package
+    (name "python-cocotb")
+    (version "1.9.2")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/cocotb/cocotb")
+             (commit (string-append "v" version))))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "19mybnhqa2jz134jj8686310fniav5nldiq0y7kbgml81ppai87c"))))
+    (build-system pyproject-build-system)
+    (arguments
+     `(#:phases (modify-phases %standard-phases
+                  (replace 'check
+                    (lambda* (#:key tests? inputs outputs #:allow-other-keys)
+                      (when tests?
+                        (invoke "make" "-C" "tests")))))))
+    (native-inputs (list python-setuptools python-wheel python-pytest))
+    (propagated-inputs (list python-find-libpython))
+    (inputs (list iverilog ghdl-clang)) ; tests
+    (home-page "https://github.com/cocotb/cocotb")
+    (synopsis "Library for writing HDL testbenches in Python")
+    (description "Coroutine based cosimulation testbench environment for
+verifying VHDL and Verilog RTL using Python.")
+    (license license:bsd-3)))
+
 (define-public python-pyvhdlmodel
   (package
     (name "python-pyvhdlmodel")