qp_gc9107_opcodes.h (7054B)
1 // Copyright 2024 Fernando Birra 2 // SPDX-License-Identifier: GPL-2.0-or-later 3 #pragma once 4 5 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 6 // Quantum Painter GC9107 command opcodes 7 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 8 9 #define GC9107_GET_POWER_MODE 0x0A // Get power mode 10 #define GC9107_GET_MADCTL 0x0B // Get MADCTL 11 #define GC9107_GET_PIXEL_FMT 0x0C // Get pixel format 12 #define GC9107_GET_IMAGE_FMT 0x0D // Get image format 13 #define GC9107_GET_SIGNAL_MODE 0x0E // Get signal mode 14 #define GC9107_GET_DIAG_RESULT 0x0F // Get self-diagnostic results 15 16 #define GC9107_SET_FRAME_RATE 0xA8 // Set frame rate 17 #define GC9107_SET_COMPLEMENT_RGB 0xAC // Set complement Principle RGB 18 #define GC9107_SET_BLANK_PORCH 0xAD // Set blank porch control, 0;front_porch[6:0],0;back_porch[6:0] 19 #define GC9107_SET_FUNCTION_CTL1 0xB1 // Set access to AVDD_VCL_CLK and VGH_VGL_CLK commands 20 #define GC9107_SET_FUNCTION_CTL2 0xB2 // Set access to VGH, VGH control commands 21 #define GC9107_SET_FUNCTION_CTL3 0xB3 // Set access to Gamma control commands 22 #define GC9107_SET_DISPLAY_INVERSION 0xB4 // Set Display Inversion control 23 #define GC9107_SET_FUNCTION_CTL6 0xB6 // Set access to commands SET_FRAME_RATE, SET_COMPLEMENT_RGB and SET_BLANK_PORCH 24 #define GC9107_SET_CUSTOM_ID_INFO 0xD3 // Set customized display id information 25 #define GC9107_AVDD_VCL_CLK 0xE3 // AVDD_CLK 26 #define GC9107_SET_VGH 0xE8 // Set VGH 27 #define GC9107_SET_VGL 0xE9 // Set VGL 28 #define GC9107_SET_VGH_VGL_CLK 0xEA // Set VGH and VGL clock divisors 29 30 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 31 // GC9107 Parameter constants 32 33 // Parameter values for 34 // GC9107_SET_PIXEL_FORMAT 35 #define GC9107_PIXEL_FORMAT_12_BPP_IFPF (0b001 << 0) // 12 bits per pixel 36 #define GC9107_PIXEL_FORMAT_16_BPP_IFPF (0b101 << 0) // 16 bits per pixel 37 #define GC9107_PIXEL_FORMAT_18_BPP_IFPB (0b110 << 0) // 18 bits per pixel 38 39 // Parameter values for 40 // GC9107_SET_COMPLEMENT_RGB 41 #define GC9107_COMPLEMENT_WITH_0 0x00 // R0 <- B0 <- 0, except if data is FFh 42 #define GC9107_COMPLEMENT_WITH_1 0x40 // R0 <- B0 <- 1, except if data is 00h 43 #define GC9107_COMPLEMENT_WITH_MSB 0x80 // R0 <- R5, B0 <- B5 44 #define GC9107_COMPLEMENT_WITH_LSB 0xC0 // R0 <- B0 <- G0 45 // Parameter masks for 46 // GC9107_SET_FUNCTION_CTL1 47 #define GC9107_ALLOW_AVDD_VCL_CLK 0b00001000 // Allow AVDD_VCL_CLK command 48 // Parameter masks for 49 // GC9107_SET_FUNCTION_CTL2 50 #define GC9107_ALLOW_SET_VGH 0b00000001 // Allow GC9107_SET_VGH 51 #define GC9107_ALLOW_SET_VGL 0b00000010 // Allow GC9107_SET_VGL 52 #define GC9107_ALLOW_SET_VGH_VGL_CLK 0b00000100 // Allow GC9107_SET_VGH_VGL_CLK 53 // Parameter masks for 54 // GC9107_SET_FUNCTION_CTL3 55 #define GC9107_ALLOW_SET_GAMMA1 0b00000001 // Allow GC9107_SET_GAMMA1 56 #define GC9107_ALLOW_SET_GAMMA2 0b00000010 // Allow GC9107_SET_GAMMA2 57 // Parameter mask for 58 // GC9107_SET_FUNCTION_CTL6 59 #define GC9107_ALLOW_SET_FRAMERATE 0b000000001 // Allow GC9107_SET_FRAME_RATE 60 #define GC9107_ALLOW_SET_COMPLEMENT_RGB 0b000010000 // Allow GC9107_SET_COMPLEMENT_RGB 61 #define GC9107_ALLOW_SET_BLANK_PORCH 0b000100000 // Allow GFC9107_SET_BLANK_PORCH 62 // Parameter values for 63 // AVDD_CLK_AD part (Most significant nibble) 64 #define GC9107_AVDD_CLK_AD_2T 0x00 65 #define GC9107_AVDD_CLK_AD_3T 0x10 66 #define GC9107_AVDD_CLK_AD_4T 0x20 67 #define GC9107_AVDD_CLK_AD_5T 0x30 68 #define GC9107_AVDD_CLK_AD_6T 0x40 69 #define GC9107_AVDD_CLK_AD_7T 0x50 70 #define GC9107_AVDD_CLK_AD_8T 0x60 71 #define GC9107_AVDD_CLK_AD_9T 0x70 72 // Parameter values for 73 // VCL_CLK_AD part (Least significant nibble) 74 #define GC9107_VCL_CLK_AD_2T 0x00 75 #define GC9107_VCL_CLK_AD_3T 0x01 76 #define GC9107_VCL_CLK_AD_4T 0x02 77 #define GC9107_VCL_CLK_AD_5T 0x03 78 #define GC9107_VCL_CLK_AD_6T 0x04 79 #define GC9107_VCL_CLK_AD_7T 0x05 80 #define GC9107_VCL_CLK_AD_8T 0x06 81 #define GC9107_VCL_CLK_AD_9T 0x07 82 // Parameter values for 83 // GC9107_SET_VGH 84 #define GC9107_VGH_P100 0x20 // +10 V 85 #define GC9107_VGH_P110 0x21 // +11 V 86 #define GC9107_VGH_P120 0x22 // +12 V 87 #define GC9107_VGH_P130 0x23 // +13 V 88 #define GC9107_VGH_P140 0x24 // +14 V 89 #define GC9107_VGH_P150 0x25 // +15 V 90 // Parameter values for 91 // GC9107_SET_VGL 92 #define VGL_N_075 0x40 // -7.5 V 93 #define VGL_N_085 0x41 // -8.5 V 94 #define VGL_N_095 0x42 // -9.5 V 95 #define VGL_N_100 0x43 // -10.0 V 96 #define VGL_N_105 0x44 // -10.5 V 97 #define VGL_N_110 0x45 // -11.0 V 98 #define VGL_N_120 0x46 // -12.0 V 99 #define VGL_N_130 0x47 // -13.0 V 100 // Parameter masks for 101 // GC9107_SET_VGH_VGL_CLK (VGH Divisor) 102 #define GC9107_VGH_CLK_DIV_2 0x00 // Clock divisor = 2 -> 6.0 Mhz 103 #define GC9107_VGH_CLK_DIV_3 0x10 // Clock divisor = 3 -> 4.0 Mhz 104 #define GC9107_VGH_CLK_DIV_4 0x20 // Clock divisor = 4 -> 3.0 Mhz 105 #define GC9107_VGH_CLK_DIV_5 0x30 // Clock divisor = 5 -> 2.4 Mhz 106 #define GC9107_VGH_CLK_DIV_6 0x40 // Clock divisor = 6 -> 2.0 Mhz 107 #define GC9107_VGH_CLK_DIV_7 0x50 // Clock divisor = 7 -> 1.7 Mhz 108 #define GC9107_VGH_CLK_DIV_8 0x60 // Clock divisor = 8 -> 1.5 Mhz 109 #define GC9107_VGH_CLK_DIV_9 0x70 // Clock divisor = 9 -> 1.3 Mhz 110 #define GC9107_VGH_CLK_DIV_10 0x80 // Clock divisor = 10 -> 1.2 Mhz 111 #define GC9107_VGH_CLK_DIV_12 0x90 // Clock divisor = 12 -> 1.0 Mhz 112 #define GC9107_VGH_CLK_DIV_15 0xA0 // Clock divisor = 15 -> 0.8 Mhz 113 #define GC9107_VGH_CLK_DIV_20 0xB0 // Clock divisor = 20 -> 0.6 Mhz 114 #define GC9107_VGH_CLK_DIV_24 0xC0 // Clock divisor = 24 -> 0.5 Mhz 115 #define GC9107_VGH_CLK_DIV_30 0xD0 // Clock divisor = 30 -> 0.4 Mhz 116 #define GC9107_VGH_CLK_DIV_40 0xE0 // Clock divisor = 40 -> 0.3 Mhz 117 #define GC9107_VGH_CLK_DIV_60 0xE0 // Clock divisor = 40 -> 0.2 Mhz 118 // Parameter masks for 119 // GC9107_SET_VGH_VGL_CLK (VGL Divisor) 120 #define GC9107_VGL_CLK_DIV_2 0x00 // Clock divisor = 2 -> 6.0 Mhz 121 #define GC9107_VGL_CLK_DIV_3 0x01 // Clock divisor = 3 -> 4.0 Mhz 122 #define GC9107_VGL_CLK_DIV_4 0x02 // Clock divisor = 4 -> 3.0 Mhz 123 #define GC9107_VGL_CLK_DIV_5 0x03 // Clock divisor = 5 -> 2.4 Mhz 124 #define GC9107_VGL_CLK_DIV_6 0x04 // Clock divisor = 6 -> 2.0 Mhz 125 #define GC9107_VGL_CLK_DIV_7 0x05 // Clock divisor = 7 -> 1.7 Mhz 126 #define GC9107_VGL_CLK_DIV_8 0x06 // Clock divisor = 8 -> 1.5 Mhz 127 #define GC9107_VGL_CLK_DIV_9 0x07 // Clock divisor = 9 -> 1.3 Mhz 128 #define GC9107_VGL_CLK_DIV_10 0x08 // Clock divisor = 10 -> 1.2 Mhz 129 #define GC9107_VGL_CLK_DIV_12 0x09 // Clock divisor = 12 -> 1.0 Mhz 130 #define GC9107_VGL_CLK_DIV_15 0x0A // Clock divisor = 15 -> 0.8 Mhz 131 #define GC9107_VGL_CLK_DIV_20 0x0B // Clock divisor = 20 -> 0.6 Mhz 132 #define GC9107_VGL_CLK_DIV_24 0x0C // Clock divisor = 24 -> 0.5 Mhz 133 #define GC9107_VGL_CLK_DIV_30 0x0D // Clock divisor = 30 -> 0.4 Mhz 134 #define GC9107_VGL_CLK_DIV_40 0x0E // Clock divisor = 40 -> 0.3 Mhz 135 #define GC9107_VGL_CLK_DIV_60 0x0E // Clock divisor = 40 -> 0.2 Mhz