qmk_firmware

QMK firmware for my keyboards (Corne, Sweep Ferris) and trackball (Ploopy Adept)
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adns5050.c (7353B)


      1 /* Copyright 2021 Colin Lam (Ploopy Corporation)
      2  * Copyright 2020 Christopher Courtney, aka Drashna Jael're  (@drashna) <drashna@live.com>
      3  * Copyright 2019 Sunjun Kim
      4  * Copyright 2019 Hiroyuki Okada
      5  *
      6  * This program is free software: you can redistribute it and/or modify
      7  * it under the terms of the GNU General Public License as published by
      8  * the Free Software Foundation, either version 2 of the License, or
      9  * (at your option) any later version.
     10  *
     11  * This program is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14  * GNU General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU General Public License
     17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
     18  */
     19 
     20 #include "adns5050.h"
     21 #include "wait.h"
     22 #include "debug.h"
     23 #include "gpio.h"
     24 #include "pointing_device_internal.h"
     25 
     26 // Registers
     27 // clang-format off
     28 #define REG_PRODUCT_ID     0x00
     29 #define REG_REVISION_ID    0x01
     30 #define REG_MOTION         0x02
     31 #define REG_DELTA_X        0x03
     32 #define REG_DELTA_Y        0x04
     33 #define REG_SQUAL          0x05
     34 #define REG_SHUTTER_UPPER  0x06
     35 #define REG_SHUTTER_LOWER  0x07
     36 #define REG_MAXIMUM_PIXEL  0x08
     37 #define REG_PIXEL_SUM      0x09
     38 #define REG_MINIMUM_PIXEL  0x0a
     39 #define REG_PIXEL_GRAB     0x0b
     40 #define REG_MOUSE_CONTROL  0x0d
     41 #define REG_MOUSE_CONTROL2 0x19
     42 #define REG_LED_DC_MODE    0x22
     43 #define REG_CHIP_RESET     0x3a
     44 #define REG_PRODUCT_ID2    0x3e
     45 #define REG_INV_REV_ID     0x3f
     46 #define REG_MOTION_BURST   0x63
     47 // clang-format on
     48 
     49 const pointing_device_driver_t adns5050_pointing_device_driver = {
     50     .init       = adns5050_init,
     51     .get_report = adns5050_get_report,
     52     .set_cpi    = adns5050_set_cpi,
     53     .get_cpi    = adns5050_get_cpi,
     54 };
     55 
     56 static bool powered_down = false;
     57 
     58 bool adns5050_init(void) {
     59     // Initialize the ADNS serial pins.
     60     gpio_set_pin_output(ADNS5050_SCLK_PIN);
     61     gpio_set_pin_output(ADNS5050_SDIO_PIN);
     62     gpio_set_pin_output(ADNS5050_CS_PIN);
     63 
     64     // reboot the adns.
     65     // if the adns hasn't initialized yet, this is harmless.
     66     adns5050_write_reg(REG_CHIP_RESET, 0x5a);
     67 
     68     // wait maximum time before adns is ready.
     69     // this ensures that the adns is actuall ready after reset.
     70     wait_ms(55);
     71 
     72     powered_down = false;
     73 
     74     // read a burst from the adns and then discard it.
     75     // gets the adns ready for write commands
     76     // (for example, setting the dpi).
     77     adns5050_read_burst();
     78 
     79     return adns5050_check_signature();
     80 }
     81 
     82 // Perform a synchronization with the ADNS.
     83 // Just as with the serial protocol, this is used by the slave to send a
     84 // synchronization signal to the master.
     85 void adns5050_sync(void) {
     86     gpio_write_pin_low(ADNS5050_CS_PIN);
     87     wait_us(1);
     88     gpio_write_pin_high(ADNS5050_CS_PIN);
     89 }
     90 
     91 void adns5050_cs_select(void) {
     92     gpio_write_pin_low(ADNS5050_CS_PIN);
     93 }
     94 
     95 void adns5050_cs_deselect(void) {
     96     gpio_write_pin_high(ADNS5050_CS_PIN);
     97 }
     98 
     99 uint8_t adns5050_serial_read(void) {
    100     gpio_set_pin_input(ADNS5050_SDIO_PIN);
    101     uint8_t byte = 0;
    102 
    103     for (uint8_t i = 0; i < 8; ++i) {
    104         gpio_write_pin_low(ADNS5050_SCLK_PIN);
    105         wait_us(1);
    106 
    107         byte = (byte << 1) | gpio_read_pin(ADNS5050_SDIO_PIN);
    108 
    109         gpio_write_pin_high(ADNS5050_SCLK_PIN);
    110         wait_us(1);
    111     }
    112 
    113     return byte;
    114 }
    115 
    116 void adns5050_serial_write(uint8_t data) {
    117     gpio_set_pin_output(ADNS5050_SDIO_PIN);
    118 
    119     for (int8_t b = 7; b >= 0; b--) {
    120         gpio_write_pin_low(ADNS5050_SCLK_PIN);
    121 
    122         if (data & (1 << b))
    123             gpio_write_pin_high(ADNS5050_SDIO_PIN);
    124         else
    125             gpio_write_pin_low(ADNS5050_SDIO_PIN);
    126 
    127         wait_us(2);
    128 
    129         gpio_write_pin_high(ADNS5050_SCLK_PIN);
    130     }
    131 
    132     // tSWR. See page 15 of the ADNS spec sheet.
    133     // Technically, this is only necessary if the next operation is an SDIO
    134     // read. This is not guaranteed to be the case, but we're being lazy.
    135     wait_us(4);
    136 
    137     // Note that tSWW is never necessary. All write operations require at
    138     // least 32us, which exceeds tSWW, so there's never a need to wait for it.
    139 }
    140 
    141 // Read a byte of data from a register on the ADNS.
    142 // Don't forget to use the register map (as defined in the header file).
    143 uint8_t adns5050_read_reg(uint8_t reg_addr) {
    144     adns5050_cs_select();
    145 
    146     adns5050_serial_write(reg_addr);
    147 
    148     // We don't need a minimum tSRAD here. That's because a 4ms wait time is
    149     // already included in adns5050_serial_write(), so we're good.
    150     // See page 10 and 15 of the ADNS spec sheet.
    151     // wait_us(4);
    152 
    153     uint8_t byte = adns5050_serial_read();
    154 
    155     // tSRW & tSRR. See page 15 of the ADNS spec sheet.
    156     // Technically, this is only necessary if the next operation is an SDIO
    157     // read or write. This is not guaranteed to be the case.
    158     // Honestly, this wait could probably be removed.
    159     wait_us(1);
    160 
    161     adns5050_cs_deselect();
    162 
    163     return byte;
    164 }
    165 
    166 void adns5050_write_reg(uint8_t reg_addr, uint8_t data) {
    167     adns5050_cs_select();
    168     adns5050_serial_write(0b10000000 | reg_addr);
    169     adns5050_serial_write(data);
    170     adns5050_cs_deselect();
    171 }
    172 
    173 report_adns5050_t adns5050_read_burst(void) {
    174     adns5050_cs_select();
    175 
    176     report_adns5050_t data;
    177     data.dx = 0;
    178     data.dy = 0;
    179 
    180     if (powered_down) {
    181         return data;
    182     }
    183 
    184     adns5050_serial_write(REG_MOTION_BURST);
    185 
    186     // We don't need a minimum tSRAD here. That's because a 4ms wait time is
    187     // already included in adns5050_serial_write(), so we're good.
    188     // See page 10 and 15 of the ADNS spec sheet.
    189     // wait_us(4);
    190 
    191     uint8_t x = adns5050_serial_read();
    192     uint8_t y = adns5050_serial_read();
    193 
    194     // Burst mode returns a bunch of other shit that we don't really need.
    195     // Setting CS to high ends burst mode early.
    196     adns5050_cs_deselect();
    197 
    198     data.dx = convert_twoscomp(x);
    199     data.dy = convert_twoscomp(y);
    200 
    201     return data;
    202 }
    203 
    204 // Convert a two's complement byte from an unsigned data type into a signed
    205 // data type.
    206 int8_t convert_twoscomp(uint8_t data) {
    207     if ((data & 0x80) == 0x80)
    208         return -128 + (data & 0x7F);
    209     else
    210         return data;
    211 }
    212 
    213 // Don't forget to use the definitions for CPI in the header file.
    214 void adns5050_set_cpi(uint16_t cpi) {
    215     uint8_t cpival = constrain((cpi / 125), 0x1, 0xD); // limits to 0--119
    216 
    217     adns5050_write_reg(REG_MOUSE_CONTROL2, 0b10000 | cpival);
    218 }
    219 
    220 uint16_t adns5050_get_cpi(void) {
    221     uint8_t cpival = adns5050_read_reg(REG_MOUSE_CONTROL2);
    222     return (uint16_t)((cpival & 0b10000) * 125);
    223 }
    224 
    225 bool __attribute__((weak)) adns5050_check_signature(void) {
    226     uint8_t pid  = adns5050_read_reg(REG_PRODUCT_ID);
    227     uint8_t rid  = adns5050_read_reg(REG_REVISION_ID);
    228     uint8_t pid2 = adns5050_read_reg(REG_PRODUCT_ID2);
    229 
    230     return (pid == 0x12 && rid == 0x01 && pid2 == 0x26);
    231 }
    232 
    233 void adns5050_power_down(void) {
    234     if (!powered_down) {
    235         powered_down = true;
    236         adns5050_write_reg(REG_MOUSE_CONTROL, 0b10);
    237     }
    238 }
    239 
    240 report_mouse_t adns5050_get_report(report_mouse_t mouse_report) {
    241     report_adns5050_t data = adns5050_read_burst();
    242 
    243     if (data.dx != 0 || data.dy != 0) {
    244         pd_dprintf("Raw ] X: %d, Y: %d\n", data.dx, data.dy);
    245         mouse_report.x = (mouse_xy_report_t)data.dx;
    246         mouse_report.y = (mouse_xy_report_t)data.dy;
    247     }
    248 
    249     return mouse_report;
    250 }