cirque_pinnacle_regdefs.h (27101B)
1 // Copyright (c) 2018 Cirque Corp. Restrictions apply. See: www.cirque.com/sw-license 2 // based on https://github.com/cirque-corp/Cirque_Pinnacle_1CA027/tree/master/Additional_Examples 3 // with modifications and changes for QMK 4 // refer to documentation: Gen2 and Gen3 (Pinnacle ASIC) at https://www.cirque.com/gen2gen3-asic-details 5 6 #pragma once 7 8 // clang-format off 9 10 #define HostReg__0 (0x00) 11 #define HostReg__1 (0x01) 12 #define HostReg__2 (0x02) 13 #define HostReg__3 (0x03) 14 #define HostReg__4 (0x04) 15 #define HostReg__5 (0x05) 16 #define HostReg__6 (0x06) 17 #define HostReg__7 (0x07) 18 #define HostReg__8 (0x08) 19 #define HostReg__9 (0x09) 20 #define HostReg__10 (0x0A) 21 #define HostReg__11 (0x0B) 22 #define HostReg__12 (0x0C) 23 #define HostReg__13 (0x0D) 24 #define HostReg__14 (0x0E) 25 #define HostReg__15 (0x0F) 26 #define HostReg__16 (0x10) 27 #define HostReg__17 (0x11) 28 #define HostReg__18 (0x12) 29 #define HostReg__19 (0x13) 30 #define HostReg__20 (0x14) 31 #define HostReg__21 (0x15) 32 #define HostReg__22 (0x16) 33 #define HostReg__23 (0x17) 34 #define HostReg__24 (0x18) 35 #define HostReg__25 (0x19) 36 #define HostReg__26 (0x1A) 37 #define HostReg__27 (0x1B) 38 #define HostReg__28 (0x1C) 39 #define HostReg__29 (0x1D) 40 #define HostReg__30 (0x1E) 41 #define HostReg__31 (0x1F) 42 43 // ---------------- Register Assignments ------------------------------------- 44 45 /*--------------------------------------------------------------------------*\ 46 Chip ID / Version 47 \*--------------------------------------------------------------------------*/ 48 // Chip ID Register 49 #define HOSTREG__CHIPID HostReg__0 50 51 // Chip Version Register 52 #define HOSTREG__VERSION HostReg__1 53 54 /*--------------------------------------------------------------------------*\ 55 Status Register 56 \*--------------------------------------------------------------------------*/ 57 // Status 1 Register -- MUST BE HOSTREG__2 58 #define HOSTREG__STATUS1 HostReg__2 59 # define HOSTREG__STATUS1__DATA_READY 0x04 60 # define HOSTREG__STATUS1__COMMAND_COMPLETE 0x08 61 #define HOSTREG__STATUS1_DEFVAL 0x00 62 63 /*--------------------------------------------------------------------------*\ 64 System Config Register 65 \*--------------------------------------------------------------------------*/ 66 #define HOSTREG__SYSCONFIG1 HostReg__3 67 # define HOSTREG__SYSCONFIG1__RESET 0x01 68 # define HOSTREG__SYSCONFIG1__STANDBY 0x02 69 # define HOSTREG__SYSCONFIG1__AUTO_SLEEP 0x04 70 # define HOSTREG__SYSCONFIG1__TRACK_DISABLE 0x08 71 # define HOSTREG__SYSCONFIG1__ANYMEAS_ENABLE 0x10 72 # define HOSTREG__SYSCONFIG1__GPIO_CTRL_ENABLE 0x20 73 # define HOSTREG__SYSCONFIG1__WAKEUP_TOGGLE 0x40 74 # define HOSTREG__SYSCONFIG1__FORCE_WAKEUP 0x80 75 #define HOSTREG__SYSCONFIG1_DEFVAL 0x00 76 77 /*--------------------------------------------------------------------------*\ 78 Feed Config Registers 79 \*--------------------------------------------------------------------------*/ 80 // Feed Config Register1 81 #define HOSTREG__FEEDCONFIG1 HostReg__4 82 # define HOSTREG__FEEDCONFIG1__FEED_ENABLE 0x01 83 # define HOSTREG__FEEDCONFIG1__DATA_TYPE__REL0_ABS1 0x02 84 # define HOSTREG__FEEDCONFIG1__FILTER_DISABLE 0x04 85 # define HOSTREG__FEEDCONFIG1__X_AXIS_DISABLE 0x08 86 # define HOSTREG__FEEDCONFIG1__Y_AXIS_DISABLE 0x10 87 # define HOSTREG__FEEDCONFIG1__AXIS_FOR_Z__Y0_X1 0x20 88 # define HOSTREG__FEEDCONFIG1__X_DATA_INVERT 0x40 89 # define HOSTREG__FEEDCONFIG1__Y_DATA_INVERT 0x80 90 #define HOSTREG__FEEDCONFIG1_DEFVAL 0x00 91 92 // Feed Config Register2 93 #define HOSTREG__FEEDCONFIG2 HostReg__5 94 # define HOSTREG__FEEDCONFIG2__INTELLIMOUSE_MODE 0x01 95 # define HOSTREG__FEEDCONFIG2__ALL_TAP_DISABLE 0x02 96 # define HOSTREG__FEEDCONFIG2__SECONDARY_TAP_DISABLE 0x04 97 # define HOSTREG__FEEDCONFIG2__SCROLL_DISABLE 0x08 98 # define HOSTREG__FEEDCONFIG2__GLIDE_EXTEND_DISABLE 0x10 99 # define HOSTREG__FEEDCONFIG2__PALM_BEFORE_Z_ENABLE 0x20 100 # define HOSTREG__FEEDCONFIG2__BUTNS_46_SCROLL_5_MIDDLE 0x40 101 # define HOSTREG__FEEDCONFIG2__SWAP_XY_RELATIVE 0x80 102 #define HOSTREG__FEEDCONFIG2_DEFVAL 0x00 103 104 // Feed Config Register3 105 #define HOSTREG__FEEDCONFIG3 HostReg__6 106 # define HOSTREG__FEEDCONFIG3__BTNS_456_TO_123_IN_REL 0x01 107 # define HOSTREG__FEEDCONFIG3__DISABLE_CROSS_RATE_SMOOTHING 0x02 108 # define HOSTREG__FEEDCONFIG3__DISABLE_PALM_NERD_MEAS 0x04 109 # define HOSTREG__FEEDCONFIG3__DISABLE_NOISE_AVOIDANCE 0x08 110 # define HOSTREG__FEEDCONFIG3__DISABLE_WRAP_LOCKOUT 0x10 111 # define HOSTREG__FEEDCONFIG3__DISABLE_DYNAMIC_EMI_ADJUST 0x20 112 # define HOSTREG__FEEDCONFIG3__DISABLE_HW_EMI_DETECT 0x40 113 # define HOSTREG__FEEDCONFIG3__DISABLE_SW_EMI_DETECT 0x80 114 #define HOSTREG__FEEDCONFIG3_DEFVAL 0x00 115 116 /*--------------------------------------------------------------------------*\ 117 Calibration Config 118 \*--------------------------------------------------------------------------*/ 119 #define HOSTREG__CALCONFIG1 HostReg__7 120 # define HOSTREG__CALCONFIG1__CALIBRATE 0x01 121 # define HOSTREG__CALCONFIG1__BACKGROUND_COMP_ENABLE 0x02 122 # define HOSTREG__CALCONFIG1__NERD_COMP_ENABLE 0x04 123 # define HOSTREG__CALCONFIG1__TRACK_ERROR_COMP_ENABLE 0x08 124 # define HOSTREG__CALCONFIG1__TAP_COMP_ENABLE 0x10 125 # define HOSTREG__CALCONFIG1__PALM_ERROR_COMP_ENABLE 0x20 126 # define HOSTREG__CALCONFIG1__CALIBRATION_MATRIX_DISABLE 0x40 127 # define HOSTREG__CALCONFIG1__FORCE_PRECALIBRATION_NOISE_CHECK 0x80 128 #define HOSTREG__CALCONFIG1_DEFVAL (HOSTREG__CALCONFIG1__BACKGROUND_COMP_ENABLE | HOSTREG__CALCONFIG1__NERD_COMP_ENABLE | HOSTREG__CALCONFIG1__TRACK_ERROR_COMP_ENABLE | HOSTREG__CALCONFIG1__TAP_COMP_ENABLE | HOSTREG__CALCONFIG1__PALM_ERROR_COMP_ENABLE) 129 130 /*--------------------------------------------------------------------------*\ 131 PS2 Aux Control Register 132 \*--------------------------------------------------------------------------*/ 133 #define HOSTREG__PS2AUX_CTRL HostReg__8 134 # define HOSTREG__PS2AUX_CTRL__CMD_PASSTHRU_ENABLE 0x01 135 # define HOSTREG__PS2AUX_CTRL__SP_EXTENDED_MODE 0x02 136 # define HOSTREG__PS2AUX_CTRL__GS_DISABLE 0x04 137 # define HOSTREG__PS2AUX_CTRL__SP_DISABLE 0x08 138 # define HOSTREG__PS2AUX_CTRL__GS_COORDINATE_DISABLE 0x10 139 # define HOSTREG__PS2AUX_CTRL__SP_COORDINATE_DISABLE 0x20 140 # define HOSTREG__PS2AUX_CTRL__DISABLE_AA00_DETECT 0x40 141 # define HOSTREG__PS2AUX_CTRL__AUX_PRESENT 0x80 142 #define HOSTREG__PR2AUX_CTRL_DEFVAL 0x00 143 144 /*--------------------------------------------------------------------------*\ 145 Sample Rate Value 146 \*--------------------------------------------------------------------------*/ 147 #define HOSTREG__SAMPLERATE HostReg__9 148 # define HOSTREG__SAMPLERATE__10_SPS 0x0A 149 # define HOSTREG__SAMPLERATE__20_SPS 0x14 150 # define HOSTREG__SAMPLERATE__40_SPS 0x28 151 # define HOSTREG__SAMPLERATE__60_SPS 0x3C 152 # define HOSTREG__SAMPLERATE__80_SPS 0x50 153 # define HOSTREG__SAMPLERATE__100_SPS 0x64 154 # define HOSTREG__SAMPLERATE__200_SPS 0xC8 // 200sps not supported 155 // only for ps2 compatibility 156 // rate set to 100sps 157 #define HOSTREG__SAMPLERATE_DEFVAL HOSTREG__SAMPLERATE__100_SPS 158 159 /*--------------------------------------------------------------------------*\ 160 Z Idle Value 161 \*--------------------------------------------------------------------------*/ 162 #define HOSTREG__ZIDLE HostReg__10 163 #define HOSTREG__ZIDLE_DEFVAL 30 // 0x1E 164 165 /*--------------------------------------------------------------------------*\ 166 Z Scaler Value 167 \*--------------------------------------------------------------------------*/ 168 #define HOSTREG__ZSCALER HostReg__11 169 #define HOSTREG__ZSCALER_DEFVAL 8 // 0x08 170 171 /*--------------------------------------------------------------------------*\ 172 Sleep Interval Value 173 \*--------------------------------------------------------------------------*/ 174 #define HOSTREG__SLEEP_INTERVAL HostReg__12 175 #define HOSTREG__SLEEP_INTERVAL_DEFVAL 73 // 0x49 176 177 /*--------------------------------------------------------------------------*\ 178 Sleep Delay Value 179 \*--------------------------------------------------------------------------*/ 180 #define HOSTREG__SLEEP_DELAY HostReg__13 181 #define HOSTREG__SLEEP_DELAY_DEFVAL 39 // 0x27 182 183 /*--------------------------------------------------------------------------*\ 184 Dynamic EMI Bad Channel Count Thresholds 185 \*--------------------------------------------------------------------------*/ 186 #define HOSTREG__DYNAMIC_EMI_ADJUST_THRESHOLD HostReg__14 187 #define HOSTREG__DYNAMIC_EMI_ADJUST_THRESHOLD_DEFVAL 66 // 0x42 188 189 /*--------------------------------------------------------------------------*\ 190 Packet Registers 191 \*--------------------------------------------------------------------------*/ 192 #define HOSTREG__PACKETBYTE_0 HostReg__18 193 #define HOSTREG__PACKETBYTE_1 HostReg__19 194 #define HOSTREG__PACKETBYTE_2 HostReg__20 195 #define HOSTREG__PACKETBYTE_3 HostReg__21 196 #define HOSTREG__PACKETBYTE_4 HostReg__22 197 #define HOSTREG__PACKETBYTE_5 HostReg__23 198 199 /*--------------------------------------------------------------------------*\ 200 Port A GPIO Control 201 \*--------------------------------------------------------------------------*/ 202 #define HOSTREG__PORTA_GPIO_CTRL HostReg__24 203 #define HOSTREG__PORTA_GPIO_CTRL_DEFVAL 0xFF 204 205 /*--------------------------------------------------------------------------*\ 206 Port A GPIO Data 207 \*--------------------------------------------------------------------------*/ 208 #define HOSTREG__PORTA_GPIO_DATA HostReg__25 209 #define HOSTREG__PORTA_GPIO_DATA_DEFVAL 0x00 210 211 /*--------------------------------------------------------------------------*\ 212 Port B GPIO Control And Data 213 \*--------------------------------------------------------------------------*/ 214 215 #define HOSTREG__PORTB_GPIO_CTRL_DATA HostReg__26 216 # define HOSTREG__PORTB_GPIO_DATA__PB0 0x01 217 # define HOSTREG__PORTB_GPIO_DATA__PB1 0x02 218 # define HOSTREG__PORTB_GPIO_DATA__PB2 0x04 219 # define HOSTREG__PORTB_GPIO_CTRL__PB0 0x08 220 # define HOSTREG__PORTB_GPIO_CTRL__PB1 0x10 221 # define HOSTREG__PORTB_GPIO_CTRL__PB2 0x20 222 # define HOSTREG__PORTB_GPIO_RSVD_0 0x40 223 # define HOSTREG__PORTB_GPIO_READ1_WRITE0 0x80 224 #define HOSTREG__PORTB_GPIO_CTRL_DATA_DEFVAL (HOSTREG__PORTB_GPIO_CTRL__PB0 | HOSTREG__PORTB_GPIO_CTRL__PB1 | HOSTREG__PORTB_GPIO_CTRL__PB2) 225 226 /*--------------------------------------------------------------------------*\ 227 Extended Register Access 228 \*--------------------------------------------------------------------------*/ 229 #define HOSTREG__EXT_REG_AXS_VALUE HostReg__27 230 231 #define HOSTREG__EXT_REG_AXS_ADDR_HIGH HostReg__28 232 #define HOSTREG__EXT_REG_AXS_ADDR_LOW HostReg__29 233 234 #define HOSTREG__EXT_REG_AXS_CTRL HostReg__30 235 # define HOSTREG__EREG_AXS__READ 0x01 236 # define HOSTREG__EREG_AXS__WRITE 0x02 237 # define HOSTREG__EREG_AXS__INC_ADDR_READ 0x04 238 # define HOSTREG__EREG_AXS__INC_ADDR_WRITE 0x08 239 # define HOSTREG__EREG_AXS__RSVD_3 0x10 240 # define HOSTREG__EREG_AXS__RSVD_2 0x20 241 # define HOSTREG__EREG_AXS__RSVD_1 0x40 242 # define HOSTREG__EREG_AXS__RSVD_0 0x80 243 244 #define HOSTREG__EXT_REG_AXS_VALUE_DEFVAL 0x00 245 #define HOSTREG__EXT_REG_AXS_ADDR_HIGH_DEFVAL 0x00 246 #define HOSTREG__EXT_REG_AXS_ADDR_LOW_DEFVAL 0x00 247 #define HOSTREG__EXT_REG_AXS_CTRL_DEFVAL 0x00 248 249 /*--------------------------------------------------------------------------*\ 250 Product ID 251 \*--------------------------------------------------------------------------*/ 252 #define HOSTREG__PRODUCT_ID HostReg__31 253 254 255 256 //Some useful values 257 #define I2C_ADDRESS_DEFAULT 0x2A 258 #define FIRMWARE_ID 0x07 259 #define FIRMWARE_VERSION 0x9D 260 261 //Anymeas config options 262 //First setting is HostReg 5. This sets toggle frequency (EF) and gain. 263 //Gain is upper two bits (0xC0), frequency is lower 6 bits (0x3F) 264 #define AnyMeas_AccumBits_ElecFreq HostReg__5 265 # define ADCCNFG_ELEC_FREQ 0x3F /* Bit 4, 3, 2, 1, 0 */ 266 # define ADCCNFG_EF_0 0x02 // 500,000Hz 267 # define ADCCNFG_EF_1 0x03 // 444,444Hz 268 # define ADCCNFG_EF_2 0x04 // 400,000Hz 269 # define ADCCNFG_EF_3 0x05 // 363,636Hz 270 # define ADCCNFG_EF_4 0x06 // 333,333Hz 271 # define ADCCNFG_EF_5 0x07 // 307,692Hz 272 # define ADCCNFG_EF_6 0x09 // 267,000Hz 273 # define ADCCNFG_EF_7 0x0B // 235,000Hz 274 # define ADCCNFG_ACCUMBITSSELECT 0xC0 /* Bit 7, 6 */ 275 # define ADCCNFG_ACCBITS_17_14_0 0x00 //This is about 2x gain 276 # define ADCCNFG_ACCBITS_17_15_1 0x40 //This is about 1.6x gain 277 # define ADCCNFG_ACCBITS_17_2__80 0x80 //This is about 1.3x gain 278 # define ADCCNFG_ACCBITS_17_2__C0 0xC0 //This is lowest gain 279 //Note, all frequencies above are based on default 500ns aperture. If aperture is shorter the frequencies will be faster and if aperture is longer the frequencies will be slower. 280 281 //Next is HostReg 6. This sets the sample length. There are four possible settings to bit length. All other settings are not normally used and should be a 0. 282 #define AnyMeas_BitLength HostReg__6 283 # define ADCCTRL_BIT_LENGTH 0x03 /* Bit 1, 0 */ 284 # define ADCCTRL_SAMPLES_32 0x00 //Note: this does not work. 285 # define ADCCTRL_SAMPLES_128 0x01 286 # define ADCCTRL_SAMPLES_256 0x02 287 # define ADCCTRL_SAMPLES_512 0x03 288 # define ADCCTRL_ENABLE 0x20 /* Bit 5 */ 289 # define ADCCTRL_INT_FLAG 0x40 /* Bit 6 */ 290 # define ADCCTRL_START_BUSY 0x80 /* Bit 7 */ 291 //The smaller the sample length the faster the measurement but the lower the SNR. For high SNR requirements 512 sample length is recommended. Alternatively, multiple 128 or 256 length measurements could be averaged. 292 293 //Next is HostReg 7. This sets the sense mux. Pinnacle has 2 sense lines, Sense N and Sense P1. There is also a Sense P2 but it is not bonded out, it is only internal. 294 //Signal on Sense N will be inverted from signal on Sense P1. Other than sign inversion, signal strength should be the same. 295 #define AnyMeas_ADC_MuxControl HostReg__7 296 # define ADCMUXCTRL_SENSEP1GATE 0x01 //Enables Sense P1. Can be combined with Sense N input or exclusivly Sense P1 alone. 297 # define ADCMUXCTRL_SENSEP2GATE 0x02 //Not used. 298 # define ADCMUXCTRL_SENSENGATE 0x04 //Enables Sense N. Can be combined with Sense P inputs or exclusivly Sense N alone. 299 # define ADCMUXCTRL_REF0GATE 0x08 //This enables the RefCap0. This is a capacitor inside the chip that is roughly 0.25pF. It is also controlled with the toggle and polarity bits so those bits must be set properly as well in order to use it. 300 # define ADCMUXCTRL_REF1GATE 0x10 //This enables the RefCap1. This is a capacitor inside the chip that is roughly 0.5pF. It is also controlled with the toggle and polarity bits so those bits must be set properly as well in order to use it. 301 # define ADCMUXCTRL_OSCMEASEN 0x80 //this is a test mode for measuring the internal oscillator. It is for IC test only. 302 303 //Next is HostReg 8. This contains various ADC config settings that are not likely to be used. 304 #define AnyMeas_ADC_Config2 HostReg__8 305 # define ADCCNFG2_ADC_CLK_SELECT 0x01 /* Bit 0 */ //If 0 use the standard 8Mhz clock. If 1 use a divide by 2, 4Mhz clock. Only used if extra slow toggle frequencies are required. 306 # define ADCCNFG2_EMI_FLAG 0x02 /* Bit 1 */ //EMI flag threshold only used with internal FW. Not valid in anymeas mode. 307 # define ADCCNFG2_EMI_FLAG_THRESHOLD_0 0x04 /* Bit 2 */ //EMI flag threshold only used with internal FW. Not valid in anymeas mode. 308 # define ADCCNFG2_EMI_FLAG_THRESHOLD_1 0x08 /* Bit 3 */ //EMI flag threshold only used with internal FW. Not valid in anymeas mode. 309 # define ADCCNFG2_DSX2_EXTEND 0x10 /* Bit 4 */ //extend one signal on the receive. Could also be helpful in situations where sensor cap is extremely high. 310 # define ADCCNFG2_ETOGGLE_DELAY 0x20 /* Bit 5 */ //delay a bit before toggling electrodes. Could be helpful in situations where sensor cap is extremely high. 311 312 //Next is HostReg 9. This sets the aperture length. Bottom 4 bits set the aperture width 313 #define AnyMeas_ADC_AWidth HostReg__9 314 # define ADCAWIDTH_AWIDTHMASK 0x0F 315 # define ADCAWIDTH_APERTURE_OPEN 0x00 //does not work 316 # define ADCAWIDTH_APERTURE_125NS 0x01 //does not work 317 # define ADCAWIDTH_APERTURE_250NS 0x02 318 # define ADCAWIDTH_APERTURE_375NS 0x03 319 # define ADCAWIDTH_APERTURE_500NS 0x04 320 # define ADCAWIDTH_APERTURE_625NS 0x05 321 # define ADCAWIDTH_APERTURE_750NS 0x06 322 # define ADCAWIDTH_APERTURE_875NS 0x07 323 # define ADCAWIDTH_APERTURE_1000NS 0x08 324 # define ADCAWIDTH_APERTURE_1125NS 0x09 325 # define ADCAWIDTH_APERTURE_1250NS 0x0A 326 # define ADCAWIDTH_APERTURE_1375NS 0x0B 327 # define ADCAWIDTH_APERTURE_1500NS 0x0C 328 # define ADCAWIDTH_APERTURE_1625NS 0x0D 329 # define ADCAWIDTH_APERTURE_1750NS 0x0E 330 # define ADCAWIDTH_APERTURE_1875NS 0x0F 331 # define ADCAWIDTH_AWIDTHPLUSHALF 0x10 332 # define ADCAWIDTH_AOPEN 0x20 333 # define ADCAWIDTH_W2WAIT 0x40 334 335 //next two registers give the high and low bytes to the 16 bit address where Pinnacle will pull the measurement data. Normally these addresses are within the base 32 registers. 336 #define AnyMeas_pADCMeasInfoStart_High_Byte HostReg__10 337 #define AnyMeas_pADCMeasInfoStart_Low_Byte HostReg__11 338 339 //Next is the measurement index, this sets the measurement state machine to the start and should be a 0 at start. 340 #define AnyMeas_MeasIndex HostReg__12 341 # define ANYMEASSTATE_RESET_START 0x00 342 # define ANYMEASSTATE_START_MEASUREMENT 0x01 343 # define ANYMEASSTATE_WAIT_FOR_MEASUREMENT_AND_HOST 0x02 344 345 //next is the state itself of the measurement, should always be 0. 346 #define AnyMeas_State HostReg__13 347 348 //next is the number of measurements. Use 0x80 to repeat the single measurement or repeat a number of measurements. 349 //0x40 will turn the ADC off after measurements. This will result in longer startup time for a subsequent measurement, but lower idle power draw. 350 #define AnyMeas_Control_NumMeas HostReg__14 351 # define ANYMEAS_CONTROL__NUM_MEAS_MASK 0x3F 352 # define ANYMEAS_CONTROL__ADC_POST_MEAS_PWR 0x40 353 # define ANYMEAS_CONTROL__REPEAT 0x80 354 355 //These are not used 356 #define AnyMeas_pADCMeasInfo_High_Byte HostReg__15 357 #define AnyMeas_pADCMeasInfo_Low_Byte HostReg__16 358 359 //16 bit result of measurement will be found in these two registers. 360 #define AnyMeas_Result_High_Byte HostReg__17 361 #define AnyMeas_Result_Low_Byte HostReg__18 362 363 // ---------------- Extended Register Assignments ---------------------------- 364 /*--------------------------------------------------------------------------*\ 365 ADC Mux Control 366 \*--------------------------------------------------------------------------*/ 367 #define EXTREG__ADCMUX_CTRL 0x00EB 368 # define EXTREG__ADCMUX_CTRL__SNSP_ENABLE 0x01 369 # define EXTREG__ADCMUX_CTRL__SNSN_ENABLE 0x04 370 371 /*--------------------------------------------------------------------------*\ 372 Timer Reload Registers 373 \*--------------------------------------------------------------------------*/ 374 #define EXTREG__PACKET_TIMER_RELOAD 0x019F 375 #define EXTREG__TRACK_TIMER_RELOAD 0x019E 376 // These two registers should have matching content. 377 # define EXTREG__TIMER_RELOAD__300_SPS 0x06 378 # define EXTREG__TIMER_RELOAD__200_SPS 0x09 379 # define EXTREG__TIMER_RELOAD__100_SPS 0x13 380 381 /*--------------------------------------------------------------------------*\ 382 Track ADC Config 383 \*--------------------------------------------------------------------------*/ 384 #define EXTREG__TRACK_ADCCONFIG 0x0187 385 // ADC-attenuation settings (held in BIT_7 and BIT_6) 386 // 1X = most sensitive, 4X = least sensitive 387 # define EXTREG__TRACK_ADCCONFIG__ADC_ATTENUATE_MASK 0xC0 388 # define EXTREG__TRACK_ADCCONFIG__ADC_ATTENUATE_1X 0x00 389 # define EXTREG__TRACK_ADCCONFIG__ADC_ATTENUATE_2X 0x40 390 # define EXTREG__TRACK_ADCCONFIG__ADC_ATTENUATE_3X 0x80 391 # define EXTREG__TRACK_ADCCONFIG__ADC_ATTENUATE_4X 0xC0 392 #define EXTREG__TRACK_ADCCONFIG_DEFVAL 0x4E 393 394 395 /*--------------------------------------------------------------------------*\ 396 Tune Edge Sensitivity 397 \*--------------------------------------------------------------------------*/ 398 // These registers are not detailed in any publically available documentation 399 // Names inferred from debug prints in https://github.com/cirque-corp/Cirque_Pinnacle_1CA027/blob/master/Circular_Trackpad 400 #define EXTREG__XAXIS_WIDEZMIN 0x0149 401 #define EXTREG__YAXIS_WIDEZMIN 0x0168 402 #define EXTREG__XAXIS_WIDEZMIN_DEFVAL 0x06 403 #define EXTREG__YAXIS_WIDEZMIN_DEFVAL 0x05 404 405 // clang-format on