mcuconf.h (6900B)
1 /* 2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio 3 Licensed under the Apache License, Version 2.0 (the "License"); 4 you may not use this file except in compliance with the License. 5 You may obtain a copy of the License at 6 http://www.apache.org/licenses/LICENSE-2.0 7 Unless required by applicable law or agreed to in writing, software 8 distributed under the License is distributed on an "AS IS" BASIS, 9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10 See the License for the specific language governing permissions and 11 limitations under the License. 12 */ 13 14 #ifndef MCUCONF_H 15 #define MCUCONF_H 16 17 /* 18 * STM32F0xx drivers configuration. 19 * The following settings override the default settings present in 20 * the various device driver implementation headers. 21 * Note that the settings for each driver only have effect if the whole 22 * driver is enabled in halconf.h. 23 * 24 * IRQ priorities: 25 * 3...0 Lowest...Highest. 26 * 27 * DMA priorities: 28 * 0...3 Lowest...Highest. 29 */ 30 31 #define STM32F0xx_MCUCONF 32 33 /* 34 * HAL driver system settings. 35 */ 36 #define STM32_NO_INIT FALSE 37 #define STM32_PVD_ENABLE FALSE 38 #define STM32_PLS STM32_PLS_LEV0 39 #define STM32_HSI_ENABLED TRUE 40 #define STM32_HSI14_ENABLED TRUE 41 #define STM32_HSI48_ENABLED FALSE 42 #define STM32_LSI_ENABLED TRUE 43 #define STM32_HSE_ENABLED FALSE 44 #define STM32_LSE_ENABLED FALSE 45 #define STM32_SW STM32_SW_PLL 46 #define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 47 #define STM32_PREDIV_VALUE 1 48 #define STM32_PLLMUL_VALUE 12 49 #define STM32_HPRE STM32_HPRE_DIV1 50 #define STM32_PPRE STM32_PPRE_DIV1 51 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK 52 #define STM32_MCOPRE STM32_MCOPRE_DIV1 53 #define STM32_PLLNODIV STM32_PLLNODIV_DIV2 54 #define STM32_USBSW STM32_USBSW_HSI48 55 #define STM32_CECSW STM32_CECSW_HSI 56 #define STM32_I2C1SW STM32_I2C1SW_HSI 57 #define STM32_USART1SW STM32_USART1SW_PCLK 58 #define STM32_RTCSEL STM32_RTCSEL_LSI 59 60 /* 61 * IRQ system settings. 62 */ 63 #define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 64 #define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 65 #define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 66 #define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 67 #define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 68 #define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 69 70 /* 71 * ADC driver system settings. 72 */ 73 #define STM32_ADC_USE_ADC1 FALSE 74 #define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK 75 #define STM32_ADC_ADC1_DMA_PRIORITY 2 76 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 77 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) 78 79 /* 80 * GPT driver system settings. 81 */ 82 #define STM32_GPT_USE_TIM1 FALSE 83 #define STM32_GPT_USE_TIM2 FALSE 84 #define STM32_GPT_USE_TIM3 FALSE 85 #define STM32_GPT_USE_TIM14 FALSE 86 #define STM32_GPT_TIM1_IRQ_PRIORITY 2 87 #define STM32_GPT_TIM2_IRQ_PRIORITY 2 88 #define STM32_GPT_TIM3_IRQ_PRIORITY 2 89 #define STM32_GPT_TIM14_IRQ_PRIORITY 2 90 91 /* 92 * I2C driver system settings. 93 */ 94 #define STM32_I2C_USE_I2C1 FALSE 95 #define STM32_I2C_BUSY_TIMEOUT 50 96 #define STM32_I2C_I2C1_IRQ_PRIORITY 3 97 #define STM32_I2C_USE_DMA TRUE 98 #define STM32_I2C_I2C1_DMA_PRIORITY 1 99 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 100 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 101 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") 102 103 /* 104 * I2S driver system settings. 105 */ 106 #define STM32_I2S_USE_SPI1 FALSE 107 #define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ 108 STM32_I2S_MODE_RX) 109 #define STM32_I2S_SPI1_IRQ_PRIORITY 2 110 #define STM32_I2S_SPI1_DMA_PRIORITY 1 111 #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 112 #define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 113 #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") 114 115 /* 116 * ICU driver system settings. 117 */ 118 #define STM32_ICU_USE_TIM1 FALSE 119 #define STM32_ICU_USE_TIM2 FALSE 120 #define STM32_ICU_USE_TIM3 FALSE 121 #define STM32_ICU_TIM1_IRQ_PRIORITY 3 122 #define STM32_ICU_TIM2_IRQ_PRIORITY 3 123 #define STM32_ICU_TIM3_IRQ_PRIORITY 3 124 125 /* 126 * PWM driver system settings. 127 */ 128 #define STM32_PWM_USE_ADVANCED FALSE 129 #define STM32_PWM_USE_TIM1 FALSE 130 #define STM32_PWM_USE_TIM2 FALSE 131 #define STM32_PWM_USE_TIM3 FALSE 132 #define STM32_PWM_TIM1_IRQ_PRIORITY 3 133 #define STM32_PWM_TIM2_IRQ_PRIORITY 3 134 #define STM32_PWM_TIM3_IRQ_PRIORITY 3 135 136 /* 137 * SERIAL driver system settings. 138 */ 139 #define STM32_SERIAL_USE_USART1 FALSE 140 #define STM32_SERIAL_USE_USART2 TRUE 141 #define STM32_SERIAL_USART1_PRIORITY 3 142 #define STM32_SERIAL_USART2_PRIORITY 3 143 144 /* 145 * SPI driver system settings. 146 */ 147 #define STM32_SPI_USE_SPI1 FALSE 148 #define STM32_SPI_SPI1_DMA_PRIORITY 1 149 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 150 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 151 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 152 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") 153 154 /* 155 * ST driver system settings. 156 */ 157 #define STM32_ST_IRQ_PRIORITY 2 158 #define STM32_ST_USE_TIMER 2 159 160 /* 161 * UART driver system settings. 162 */ 163 #define STM32_UART_USE_USART1 FALSE 164 #define STM32_UART_USE_USART2 FALSE 165 #define STM32_UART_USART1_IRQ_PRIORITY 3 166 #define STM32_UART_USART2_IRQ_PRIORITY 3 167 #define STM32_UART_USART1_DMA_PRIORITY 0 168 #define STM32_UART_USART2_DMA_PRIORITY 0 169 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 170 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 171 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) 172 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 173 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") 174 175 /* 176 * WDG driver system settings. 177 */ 178 #define STM32_WDG_USE_IWDG FALSE 179 180 /* 181 * USB driver system settings. 182 */ 183 #define STM32_USB_USE_USB1 TRUE 184 #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE 185 #define STM32_USB_USB1_LP_IRQ_PRIORITY 3 186 187 #endif /* MCUCONF_H */