qmk_firmware

QMK firmware for my keyboards (Corne, Sweep Ferris) and trackball (Ploopy Adept)
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config.h (1650B)


      1 /*
      2 Copyright 2012 Jun Wako <wakojun@gmail.com>
      3 
      4 This program is free software: you can redistribute it and/or modify
      5 it under the terms of the GNU General Public License as published by
      6 the Free Software Foundation, either version 2 of the License, or
      7 (at your option) any later version.
      8 
      9 This program is distributed in the hope that it will be useful,
     10 but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 GNU General Public License for more details.
     13 
     14 You should have received a copy of the GNU General Public License
     15 along with this program.  If not, see <http://www.gnu.org/licenses/>.
     16 */
     17 
     18 #pragma once
     19 
     20 
     21 /* key matrix size */
     22 #define MATRIX_ROWS 16  // keycode bit: 3-0
     23 #define MATRIX_COLS 8   // keycode bit: 6-4
     24 
     25 /* key combination for command */
     26 #define IS_COMMAND() ( \
     27     get_mods() == (MOD_BIT(KC_LSFT) | MOD_BIT(KC_RSFT)) || \
     28     get_mods() == (MOD_BIT(KC_LCTL) | MOD_BIT(KC_RSFT)) \
     29 )
     30 
     31 #define XT_CLOCK_PIN D1
     32 #define XT_DATA_PIN D0
     33 #define XT_RST_PIN B7
     34 
     35 /* hard reset: low pulse for 500ms and after that HiZ for safety */
     36 #define XT_RESET() do { \
     37     gpio_write_pin_low(XT_RST_PIN); \
     38     gpio_set_pin_output(XT_RST_PIN); \
     39     wait_ms(500); \
     40     gpio_set_pin_input(XT_RST_PIN); \
     41 } while (0)
     42 
     43 /* INT1 for falling edge of clock line */
     44 #define XT_INT_INIT() do { \
     45     EICRA |= ((1 << ISC11) | (0 << ISC10)); \
     46 } while (0)
     47 
     48 /* clears flag and enables interrupt */
     49 #define XT_INT_ON() do { \
     50     EIFR  |= (1 << INTF1); \
     51     EIMSK |= (1 << INT1); \
     52 } while (0)
     53 
     54 #define XT_INT_OFF() do { \
     55     EIMSK &= ~(1 << INT1); \
     56 } while (0)
     57 
     58 #define XT_INT_VECT INT1_vect