qmk_firmware

QMK firmware for my keyboards (Corne, Sweep Ferris) and trackball (Ploopy Adept)
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config.h (1802B)


      1 // Copyright 2012 Jun Wako <wakojun@gmail.com>
      2 // Copyright 2013 Oleg Kostyuk <cub.uanic@gmail.com>
      3 // Copyright 2017 Erin Call <hello@erincall.com>
      4 // Copyright 2023 @frobiac
      5 // SPDX-License-Identifier: GPL-2.0-or-later
      6 
      7 #pragma once
      8 
      9 #define MATRIX_ROWS 10
     10 #define MATRIX_COLS 4
     11 #define EXPANDER_COL_REGISTER GPIOA
     12 #define EXPANDER_ROW_REGISTER GPIOB
     13 
     14 #ifdef PS2_MOUSE_ENABLE
     15 #    define PS2_MOUSE_USE_REMOTE_MODE
     16 #    define PS2_MOUSE_INIT_DELAY 1000
     17 #endif
     18 
     19 // clang-format off
     20 #ifdef PS2_DRIVER_USART
     21 
     22 #    define PS2_CLOCK_PIN D5
     23 #    define PS2_DATA_PIN D2
     24 
     25     /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
     26     /* set DDR of CLOCK as input to be slave */
     27     #define PS2_USART_INIT() do {   \
     28         PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT);   \
     29         PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT);     \
     30         UCSR1C = ((1 << UMSEL10) |  \
     31                   (3 << UPM10)   |  \
     32                   (0 << USBS1)   |  \
     33                   (3 << UCSZ10)  |  \
     34                   (0 << UCPOL1));   \
     35         UCSR1A = 0;                 \
     36         UBRR1H = 0;                 \
     37         UBRR1L = 0;                 \
     38     } while (0)
     39     #define PS2_USART_RX_INT_ON() do {  \
     40         UCSR1B = ((1 << RXCIE1) |       \
     41                   (1 << RXEN1));        \
     42     } while (0)
     43     #define PS2_USART_RX_POLL_ON() do { \
     44         UCSR1B = (1 << RXEN1);          \
     45     } while (0)
     46     #define PS2_USART_OFF() do {    \
     47         UCSR1C = 0;                 \
     48         UCSR1B &= ~((1 << RXEN1) |  \
     49                     (1 << TXEN1));  \
     50     } while (0)
     51     #define PS2_USART_RX_READY      (UCSR1A & (1<<RXC1))
     52     #define PS2_USART_RX_DATA       UDR1
     53     #define PS2_USART_ERROR         (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
     54     #define PS2_USART_RX_VECT       USART1_RX_vect
     55 #endif
     56