mcuconf.h (15429B)
1 /* 2 ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio 3 4 Licensed under the Apache License, Version 2.0 (the "License"); 5 you may not use this file except in compliance with the License. 6 You may obtain a copy of the License at 7 8 http://www.apache.org/licenses/LICENSE-2.0 9 10 Unless required by applicable law or agreed to in writing, software 11 distributed under the License is distributed on an "AS IS" BASIS, 12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 See the License for the specific language governing permissions and 14 limitations under the License. 15 */ 16 17 #ifndef MCUCONF_H 18 #define MCUCONF_H 19 20 /* 21 * STM32F4xx drivers configuration. 22 * The following settings override the default settings present in 23 * the various device driver implementation headers. 24 * Note that the settings for each driver only have effect if the whole 25 * driver is enabled in halconf.h. 26 * 27 * IRQ priorities: 28 * 15...0 Lowest...Highest. 29 * 30 * DMA priorities: 31 * 0...3 Lowest...Highest. 32 */ 33 34 #define STM32F4xx_MCUCONF 35 #define STM32F446_MCUCONF 36 37 /* 38 * HAL driver system settings. 39 */ 40 #define STM32_NO_INIT FALSE 41 #define STM32_PVD_ENABLE FALSE 42 #define STM32_PLS STM32_PLS_LEV0 43 #define STM32_BKPRAM_ENABLE FALSE 44 #define STM32_HSI_ENABLED FALSE 45 #define STM32_LSI_ENABLED TRUE 46 #define STM32_HSE_ENABLED TRUE 47 #define STM32_LSE_ENABLED FALSE 48 #define STM32_CLOCK48_REQUIRED TRUE 49 #define STM32_SW STM32_SW_PLL 50 #define STM32_PLLSRC STM32_PLLSRC_HSE 51 #define STM32_PLLM_VALUE 4 52 #define STM32_PLLN_VALUE 180 53 #define STM32_PLLP_VALUE 2 54 #define STM32_PLLQ_VALUE 7 55 #define STM32_PLLI2SN_VALUE 192 56 #define STM32_PLLI2SM_VALUE 8 57 #define STM32_PLLI2SR_VALUE 4 58 #define STM32_PLLI2SP_VALUE 4 59 #define STM32_PLLI2SQ_VALUE 4 60 #define STM32_PLLSAIN_VALUE 192 61 #define STM32_PLLSAIM_VALUE 4 62 #define STM32_PLLSAIP_VALUE 8 63 #define STM32_PLLSAIQ_VALUE 4 64 #define STM32_HPRE STM32_HPRE_DIV1 65 #define STM32_PPRE1 STM32_PPRE1_DIV4 66 #define STM32_PPRE2 STM32_PPRE2_DIV2 67 #define STM32_RTCSEL STM32_RTCSEL_LSI 68 #define STM32_RTCPRE_VALUE 8 69 #define STM32_MCO1SEL STM32_MCO1SEL_HSE 70 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 71 #define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S 72 #define STM32_MCO2PRE STM32_MCO2PRE_DIV1 73 #define STM32_I2SSRC STM32_I2SSRC_PLLI2S 74 #define STM32_SAI1SEL STM32_SAI2SEL_PLLR 75 #define STM32_SAI2SEL STM32_SAI2SEL_PLLR 76 #define STM32_CK48MSEL STM32_CK48MSEL_PLLALT 77 78 /* 79 * IRQ system settings. 80 */ 81 #define STM32_IRQ_EXTI0_PRIORITY 6 82 #define STM32_IRQ_EXTI1_PRIORITY 6 83 #define STM32_IRQ_EXTI2_PRIORITY 6 84 #define STM32_IRQ_EXTI3_PRIORITY 6 85 #define STM32_IRQ_EXTI4_PRIORITY 6 86 #define STM32_IRQ_EXTI5_9_PRIORITY 6 87 #define STM32_IRQ_EXTI10_15_PRIORITY 6 88 #define STM32_IRQ_EXTI16_PRIORITY 6 89 #define STM32_IRQ_EXTI17_PRIORITY 15 90 #define STM32_IRQ_EXTI18_PRIORITY 6 91 #define STM32_IRQ_EXTI19_PRIORITY 6 92 #define STM32_IRQ_EXTI20_PRIORITY 6 93 #define STM32_IRQ_EXTI21_PRIORITY 15 94 #define STM32_IRQ_EXTI22_PRIORITY 15 95 96 #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 97 #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 98 #define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 99 #define STM32_IRQ_TIM1_CC_PRIORITY 7 100 #define STM32_IRQ_TIM2_PRIORITY 7 101 #define STM32_IRQ_TIM3_PRIORITY 7 102 #define STM32_IRQ_TIM4_PRIORITY 7 103 #define STM32_IRQ_TIM5_PRIORITY 7 104 #define STM32_IRQ_TIM6_PRIORITY 7 105 #define STM32_IRQ_TIM7_PRIORITY 7 106 #define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 107 #define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 108 #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 109 #define STM32_IRQ_TIM8_CC_PRIORITY 7 110 111 #define STM32_IRQ_USART1_PRIORITY 12 112 #define STM32_IRQ_USART2_PRIORITY 12 113 #define STM32_IRQ_USART3_PRIORITY 12 114 #define STM32_IRQ_UART4_PRIORITY 12 115 #define STM32_IRQ_UART5_PRIORITY 12 116 #define STM32_IRQ_USART6_PRIORITY 12 117 #define STM32_IRQ_UART7_PRIORITY 12 118 #define STM32_IRQ_UART8_PRIORITY 12 119 120 /* 121 * ADC driver system settings. 122 */ 123 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 124 #define STM32_ADC_USE_ADC1 FALSE 125 #define STM32_ADC_USE_ADC2 FALSE 126 #define STM32_ADC_USE_ADC3 FALSE 127 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 128 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) 129 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) 130 #define STM32_ADC_ADC1_DMA_PRIORITY 2 131 #define STM32_ADC_ADC2_DMA_PRIORITY 2 132 #define STM32_ADC_ADC3_DMA_PRIORITY 2 133 #define STM32_ADC_IRQ_PRIORITY 6 134 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 135 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 136 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 137 138 /* 139 * CAN driver system settings. 140 */ 141 #define STM32_CAN_USE_CAN1 FALSE 142 #define STM32_CAN_USE_CAN2 FALSE 143 #define STM32_CAN_CAN1_IRQ_PRIORITY 11 144 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 145 146 /* 147 * DAC driver system settings. 148 */ 149 #define STM32_DAC_DUAL_MODE FALSE 150 #define STM32_DAC_USE_DAC1_CH1 FALSE 151 #define STM32_DAC_USE_DAC1_CH2 FALSE 152 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 153 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 154 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 155 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 156 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) 157 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 158 159 /* 160 * GPT driver system settings. 161 */ 162 #define STM32_GPT_USE_TIM1 FALSE 163 #define STM32_GPT_USE_TIM2 FALSE 164 #define STM32_GPT_USE_TIM3 FALSE 165 #define STM32_GPT_USE_TIM4 FALSE 166 #define STM32_GPT_USE_TIM5 FALSE 167 #define STM32_GPT_USE_TIM6 FALSE 168 #define STM32_GPT_USE_TIM7 FALSE 169 #define STM32_GPT_USE_TIM8 FALSE 170 #define STM32_GPT_USE_TIM9 FALSE 171 #define STM32_GPT_USE_TIM10 FALSE 172 #define STM32_GPT_USE_TIM11 FALSE 173 #define STM32_GPT_USE_TIM12 FALSE 174 #define STM32_GPT_USE_TIM13 FALSE 175 #define STM32_GPT_USE_TIM14 FALSE 176 177 /* 178 * I2C driver system settings. 179 */ 180 #define STM32_I2C_USE_I2C1 FALSE 181 #define STM32_I2C_USE_I2C2 FALSE 182 #define STM32_I2C_USE_I2C3 FALSE 183 #define STM32_I2C_BUSY_TIMEOUT 50 184 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) 185 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 186 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 187 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 188 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 189 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 190 #define STM32_I2C_I2C1_IRQ_PRIORITY 5 191 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 192 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 193 #define STM32_I2C_I2C1_DMA_PRIORITY 3 194 #define STM32_I2C_I2C2_DMA_PRIORITY 3 195 #define STM32_I2C_I2C3_DMA_PRIORITY 3 196 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") 197 198 /* 199 * I2S driver system settings. 200 */ 201 #define STM32_I2S_USE_SPI2 FALSE 202 #define STM32_I2S_USE_SPI3 FALSE 203 #define STM32_I2S_SPI2_IRQ_PRIORITY 10 204 #define STM32_I2S_SPI3_IRQ_PRIORITY 10 205 #define STM32_I2S_SPI2_DMA_PRIORITY 1 206 #define STM32_I2S_SPI3_DMA_PRIORITY 1 207 #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 208 #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 209 #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) 210 #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 211 #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") 212 213 /* 214 * ICU driver system settings. 215 */ 216 #define STM32_ICU_USE_TIM1 FALSE 217 #define STM32_ICU_USE_TIM2 FALSE 218 #define STM32_ICU_USE_TIM3 FALSE 219 #define STM32_ICU_USE_TIM4 FALSE 220 #define STM32_ICU_USE_TIM5 FALSE 221 #define STM32_ICU_USE_TIM8 FALSE 222 #define STM32_ICU_USE_TIM9 FALSE 223 #define STM32_ICU_USE_TIM10 FALSE 224 #define STM32_ICU_USE_TIM11 FALSE 225 #define STM32_ICU_USE_TIM12 FALSE 226 #define STM32_ICU_USE_TIM13 FALSE 227 #define STM32_ICU_USE_TIM14 FALSE 228 229 /* 230 * MAC driver system settings. 231 */ 232 #define STM32_MAC_TRANSMIT_BUFFERS 2 233 #define STM32_MAC_RECEIVE_BUFFERS 4 234 #define STM32_MAC_BUFFERS_SIZE 1522 235 #define STM32_MAC_PHY_TIMEOUT 100 236 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE 237 #define STM32_MAC_ETH1_IRQ_PRIORITY 13 238 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 239 240 /* 241 * PWM driver system settings. 242 */ 243 #define STM32_PWM_USE_TIM1 FALSE 244 #define STM32_PWM_USE_TIM2 FALSE 245 #define STM32_PWM_USE_TIM3 FALSE 246 #define STM32_PWM_USE_TIM4 FALSE 247 #define STM32_PWM_USE_TIM5 FALSE 248 #define STM32_PWM_USE_TIM8 FALSE 249 #define STM32_PWM_USE_TIM9 FALSE 250 #define STM32_PWM_USE_TIM10 FALSE 251 #define STM32_PWM_USE_TIM11 FALSE 252 #define STM32_PWM_USE_TIM12 FALSE 253 #define STM32_PWM_USE_TIM13 FALSE 254 #define STM32_PWM_USE_TIM14 FALSE 255 256 /* 257 * RTC driver system settings. 258 */ 259 #define STM32_RTC_PRESA_VALUE 32 260 #define STM32_RTC_PRESS_VALUE 1024 261 #define STM32_RTC_CR_INIT 0 262 #define STM32_RTC_TAMPCR_INIT 0 263 264 /* 265 * SDC driver system settings. 266 */ 267 #define STM32_SDC_SDIO_DMA_PRIORITY 3 268 #define STM32_SDC_SDIO_IRQ_PRIORITY 9 269 #define STM32_SDC_WRITE_TIMEOUT_MS 1000 270 #define STM32_SDC_READ_TIMEOUT_MS 1000 271 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 272 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE 273 #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) 274 275 /* 276 * SERIAL driver system settings. 277 */ 278 #define STM32_SERIAL_USE_USART1 FALSE 279 #define STM32_SERIAL_USE_USART2 FALSE 280 #define STM32_SERIAL_USE_USART3 FALSE 281 #define STM32_SERIAL_USE_UART4 FALSE 282 #define STM32_SERIAL_USE_UART5 FALSE 283 #define STM32_SERIAL_USE_USART6 FALSE 284 #define STM32_SERIAL_USE_UART7 FALSE 285 #define STM32_SERIAL_USE_UART8 FALSE 286 287 /* 288 * SPI driver system settings. 289 */ 290 #define STM32_SPI_USE_SPI1 FALSE 291 #define STM32_SPI_USE_SPI2 FALSE 292 #define STM32_SPI_USE_SPI3 FALSE 293 #define STM32_SPI_USE_SPI4 FALSE 294 #define STM32_SPI_USE_SPI5 FALSE 295 #define STM32_SPI_USE_SPI6 FALSE 296 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) 297 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) 298 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 299 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 300 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) 301 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 302 #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) 303 #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) 304 #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) 305 #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 306 #define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) 307 #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) 308 #define STM32_SPI_SPI1_DMA_PRIORITY 1 309 #define STM32_SPI_SPI2_DMA_PRIORITY 1 310 #define STM32_SPI_SPI3_DMA_PRIORITY 1 311 #define STM32_SPI_SPI4_DMA_PRIORITY 1 312 #define STM32_SPI_SPI5_DMA_PRIORITY 1 313 #define STM32_SPI_SPI6_DMA_PRIORITY 1 314 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 315 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 316 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 317 #define STM32_SPI_SPI4_IRQ_PRIORITY 10 318 #define STM32_SPI_SPI5_IRQ_PRIORITY 10 319 #define STM32_SPI_SPI6_IRQ_PRIORITY 10 320 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") 321 322 /* 323 * ST driver system settings. 324 */ 325 #define STM32_ST_IRQ_PRIORITY 8 326 #define STM32_ST_USE_TIMER 2 327 328 /* 329 * UART driver system settings. 330 */ 331 #define STM32_UART_USE_USART1 FALSE 332 #define STM32_UART_USE_USART2 FALSE 333 #define STM32_UART_USE_USART3 FALSE 334 #define STM32_UART_USE_UART4 FALSE 335 #define STM32_UART_USE_UART5 FALSE 336 #define STM32_UART_USE_USART6 FALSE 337 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) 338 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 339 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) 340 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 341 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) 342 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 343 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 344 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 345 #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) 346 #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 347 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) 348 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 349 #define STM32_UART_USART1_DMA_PRIORITY 0 350 #define STM32_UART_USART2_DMA_PRIORITY 0 351 #define STM32_UART_USART3_DMA_PRIORITY 0 352 #define STM32_UART_UART4_DMA_PRIORITY 0 353 #define STM32_UART_UART5_DMA_PRIORITY 0 354 #define STM32_UART_USART6_DMA_PRIORITY 0 355 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") 356 357 /* 358 * USB driver system settings. 359 */ 360 #define STM32_USB_USE_OTG1 TRUE 361 #define STM32_USB_USE_OTG2 FALSE 362 #define STM32_USB_OTG1_IRQ_PRIORITY 14 363 #define STM32_USB_OTG2_IRQ_PRIORITY 14 364 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 365 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 366 #define STM32_USB_HOST_WAKEUP_DURATION 2 367 368 /* 369 * WDG driver system settings. 370 */ 371 #define STM32_WDG_USE_IWDG FALSE 372 373 #endif /* MCUCONF_H */