mcuconf.h (13389B)
1 /* 2 ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio 3 4 Licensed under the Apache License, Version 2.0 (the "License"); 5 you may not use this file except in compliance with the License. 6 You may obtain a copy of the License at 7 8 http://www.apache.org/licenses/LICENSE-2.0 9 10 Unless required by applicable law or agreed to in writing, software 11 distributed under the License is distributed on an "AS IS" BASIS, 12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 See the License for the specific language governing permissions and 14 limitations under the License. 15 */ 16 17 /* 18 * STM32G4xx drivers configuration. 19 * The following settings override the default settings present in 20 * the various device driver implementation headers. 21 * Note that the settings for each driver only have effect if the whole 22 * driver is enabled in halconf.h. 23 * 24 * IRQ priorities: 25 * 15...0 Lowest...Highest. 26 * 27 * DMA priorities: 28 * 0...3 Lowest...Highest. 29 */ 30 31 #ifndef MCUCONF_H 32 #define MCUCONF_H 33 34 #define STM32G4xx_MCUCONF 35 #define STM32G431_MCUCONF 36 #define STM32G441_MCUCONF 37 38 /* 39 * HAL driver system settings. 40 */ 41 #define STM32_NO_INIT FALSE 42 #define STM32_CLOCK_DYNAMIC FALSE 43 #define STM32_VOS STM32_VOS_RANGE1 44 #define STM32_PWR_BOOST TRUE 45 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) 46 #define STM32_PWR_CR3 (PWR_CR3_EIWF) 47 #define STM32_PWR_CR4 (0U) 48 #define STM32_PWR_PUCRA (0U) 49 #define STM32_PWR_PDCRA (0U) 50 #define STM32_PWR_PUCRB (0U) 51 #define STM32_PWR_PDCRB (0U) 52 #define STM32_PWR_PUCRC (0U) 53 #define STM32_PWR_PDCRC (0U) 54 #define STM32_PWR_PUCRD (0U) 55 #define STM32_PWR_PDCRD (0U) 56 #define STM32_PWR_PUCRE (0U) 57 #define STM32_PWR_PDCRE (0U) 58 #define STM32_PWR_PUCRF (0U) 59 #define STM32_PWR_PDCRF (0U) 60 #define STM32_PWR_PUCRG (0U) 61 #define STM32_PWR_PDCRG (0U) 62 #define STM32_HSI16_ENABLED TRUE 63 #define STM32_HSI48_ENABLED TRUE 64 #define STM32_HSE_ENABLED FALSE 65 #define STM32_LSI_ENABLED FALSE 66 #define STM32_LSE_ENABLED FALSE 67 #define STM32_SW STM32_SW_PLLRCLK 68 #define STM32_PLLSRC STM32_PLLSRC_HSI16 69 #define STM32_PLLM_VALUE 4 70 #define STM32_PLLN_VALUE 80 71 #define STM32_PLLPDIV_VALUE 0 72 #define STM32_PLLP_VALUE 7 73 #define STM32_PLLQ_VALUE 8 74 #define STM32_PLLR_VALUE 2 75 #define STM32_HPRE STM32_HPRE_DIV1 76 #define STM32_PPRE1 STM32_PPRE1_DIV1 77 #define STM32_PPRE2 STM32_PPRE2_DIV1 78 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK 79 #define STM32_MCOPRE STM32_MCOPRE_DIV1 80 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK 81 82 /* 83 * Peripherals clock sources. 84 */ 85 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK 86 #define STM32_USART2SEL STM32_USART2SEL_SYSCLK 87 #define STM32_USART3SEL STM32_USART3SEL_SYSCLK 88 #define STM32_UART4SEL STM32_UART4SEL_SYSCLK 89 #define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1 90 #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 91 #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 92 #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 93 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 94 #define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK 95 #define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK 96 #define STM32_FDCANSEL STM32_FDCANSEL_PCLK1 97 #define STM32_CLK48SEL STM32_CLK48SEL_HSI48 98 #define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK 99 #define STM32_RTCSEL STM32_RTCSEL_NOCLOCK 100 101 /* 102 * IRQ system settings. 103 */ 104 #define STM32_IRQ_EXTI0_PRIORITY 6 105 #define STM32_IRQ_EXTI1_PRIORITY 6 106 #define STM32_IRQ_EXTI2_PRIORITY 6 107 #define STM32_IRQ_EXTI3_PRIORITY 6 108 #define STM32_IRQ_EXTI4_PRIORITY 6 109 #define STM32_IRQ_EXTI5_9_PRIORITY 6 110 #define STM32_IRQ_EXTI10_15_PRIORITY 6 111 #define STM32_IRQ_EXTI164041_PRIORITY 6 112 #define STM32_IRQ_EXTI17_PRIORITY 6 113 #define STM32_IRQ_EXTI18_PRIORITY 6 114 #define STM32_IRQ_EXTI19_PRIORITY 6 115 #define STM32_IRQ_EXTI20_PRIORITY 6 116 #define STM32_IRQ_EXTI212229_PRIORITY 6 117 #define STM32_IRQ_EXTI30_32_PRIORITY 6 118 #define STM32_IRQ_EXTI33_PRIORITY 6 119 120 #define STM32_IRQ_FDCAN1_PRIORITY 10 121 122 #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 123 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 124 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 125 #define STM32_IRQ_TIM1_CC_PRIORITY 7 126 #define STM32_IRQ_TIM2_PRIORITY 7 127 #define STM32_IRQ_TIM3_PRIORITY 7 128 #define STM32_IRQ_TIM4_PRIORITY 7 129 #define STM32_IRQ_TIM6_PRIORITY 7 130 #define STM32_IRQ_TIM7_PRIORITY 7 131 #define STM32_IRQ_TIM8_UP_PRIORITY 7 132 #define STM32_IRQ_TIM8_CC_PRIORITY 7 133 134 #define STM32_IRQ_USART1_PRIORITY 12 135 #define STM32_IRQ_USART2_PRIORITY 12 136 #define STM32_IRQ_USART3_PRIORITY 12 137 #define STM32_IRQ_UART4_PRIORITY 12 138 #define STM32_IRQ_LPUART1_PRIORITY 12 139 140 /* 141 * ADC driver system settings. 142 */ 143 #define STM32_ADC_DUAL_MODE FALSE 144 #define STM32_ADC_COMPACT_SAMPLES FALSE 145 #define STM32_ADC_USE_ADC1 FALSE 146 #define STM32_ADC_USE_ADC2 FALSE 147 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY 148 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY 149 #define STM32_ADC_ADC1_DMA_PRIORITY 2 150 #define STM32_ADC_ADC2_DMA_PRIORITY 2 151 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 152 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 153 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 154 #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 155 #define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2 156 157 /* 158 * CAN driver system settings. 159 */ 160 #define STM32_CAN_USE_FDCAN1 FALSE 161 162 /* 163 * DAC driver system settings. 164 */ 165 #define STM32_DAC_DUAL_MODE FALSE 166 #define STM32_DAC_USE_DAC1_CH1 FALSE 167 #define STM32_DAC_USE_DAC1_CH2 FALSE 168 #define STM32_DAC_USE_DAC3_CH1 FALSE 169 #define STM32_DAC_USE_DAC3_CH2 FALSE 170 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 171 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 172 #define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10 173 #define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10 174 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 175 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 176 #define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2 177 #define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2 178 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY 179 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY 180 #define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY 181 #define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY 182 183 /* 184 * GPT driver system settings. 185 */ 186 #define STM32_GPT_USE_TIM1 FALSE 187 #define STM32_GPT_USE_TIM2 FALSE 188 #define STM32_GPT_USE_TIM3 FALSE 189 #define STM32_GPT_USE_TIM4 FALSE 190 #define STM32_GPT_USE_TIM6 FALSE 191 #define STM32_GPT_USE_TIM7 FALSE 192 #define STM32_GPT_USE_TIM8 FALSE 193 #define STM32_GPT_USE_TIM15 FALSE 194 #define STM32_GPT_USE_TIM16 FALSE 195 #define STM32_GPT_USE_TIM17 FALSE 196 197 /* 198 * I2C driver system settings. 199 */ 200 #define STM32_I2C_USE_I2C1 FALSE 201 #define STM32_I2C_USE_I2C2 FALSE 202 #define STM32_I2C_USE_I2C3 FALSE 203 #define STM32_I2C_BUSY_TIMEOUT 50 204 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 205 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 206 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 207 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 208 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 209 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 210 #define STM32_I2C_I2C1_IRQ_PRIORITY 5 211 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 212 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 213 #define STM32_I2C_I2C1_DMA_PRIORITY 3 214 #define STM32_I2C_I2C2_DMA_PRIORITY 3 215 #define STM32_I2C_I2C3_DMA_PRIORITY 3 216 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") 217 218 /* 219 * ICU driver system settings. 220 */ 221 #define STM32_ICU_USE_TIM1 FALSE 222 #define STM32_ICU_USE_TIM2 FALSE 223 #define STM32_ICU_USE_TIM3 FALSE 224 #define STM32_ICU_USE_TIM4 FALSE 225 #define STM32_ICU_USE_TIM8 FALSE 226 #define STM32_ICU_USE_TIM15 FALSE 227 228 /* 229 * PWM driver system settings. 230 */ 231 #define STM32_PWM_USE_TIM1 FALSE 232 #define STM32_PWM_USE_TIM2 FALSE 233 #define STM32_PWM_USE_TIM3 FALSE 234 #define STM32_PWM_USE_TIM4 FALSE 235 #define STM32_PWM_USE_TIM8 FALSE 236 #define STM32_PWM_USE_TIM15 FALSE 237 #define STM32_PWM_USE_TIM16 FALSE 238 #define STM32_PWM_USE_TIM17 FALSE 239 240 /* 241 * RTC driver system settings. 242 */ 243 #define STM32_RTC_PRESA_VALUE 32 244 #define STM32_RTC_PRESS_VALUE 1024 245 #define STM32_RTC_CR_INIT 0 246 #define STM32_TAMP_CR1_INIT 0 247 #define STM32_TAMP_CR2_INIT 0 248 #define STM32_TAMP_FLTCR_INIT 0 249 #define STM32_TAMP_IER_INIT 0 250 251 /* 252 * SDC driver system settings. 253 */ 254 255 /* 256 * SERIAL driver system settings. 257 */ 258 #define STM32_SERIAL_USE_USART1 FALSE 259 #define STM32_SERIAL_USE_USART2 FALSE 260 #define STM32_SERIAL_USE_USART3 FALSE 261 #define STM32_SERIAL_USE_UART4 FALSE 262 #define STM32_SERIAL_USE_LPUART1 FALSE 263 264 /* 265 * SIO driver system settings. 266 */ 267 #define STM32_SIO_USE_USART1 FALSE 268 #define STM32_SIO_USE_USART2 FALSE 269 #define STM32_SIO_USE_USART3 FALSE 270 #define STM32_SIO_USE_UART4 FALSE 271 #define STM32_SIO_USE_LPUART1 FALSE 272 273 /* 274 * SPI driver system settings. 275 */ 276 #define STM32_SPI_USE_SPI1 FALSE 277 #define STM32_SPI_USE_SPI2 FALSE 278 #define STM32_SPI_USE_SPI3 FALSE 279 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 280 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 281 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 282 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 283 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 284 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 285 #define STM32_SPI_SPI1_DMA_PRIORITY 1 286 #define STM32_SPI_SPI2_DMA_PRIORITY 1 287 #define STM32_SPI_SPI3_DMA_PRIORITY 1 288 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 289 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 290 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 291 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") 292 293 /* 294 * ST driver system settings. 295 */ 296 #define STM32_ST_IRQ_PRIORITY 8 297 #define STM32_ST_USE_TIMER 2 298 299 /* 300 * TRNG driver system settings. 301 */ 302 #define STM32_TRNG_USE_RNG1 FALSE 303 304 /* 305 * UART driver system settings. 306 */ 307 #define STM32_UART_USE_USART1 FALSE 308 #define STM32_UART_USE_USART2 FALSE 309 #define STM32_UART_USE_USART3 FALSE 310 #define STM32_UART_USE_UART4 FALSE 311 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 312 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 313 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 314 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 315 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 316 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 317 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 318 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY 319 #define STM32_UART_USART1_DMA_PRIORITY 0 320 #define STM32_UART_USART2_DMA_PRIORITY 0 321 #define STM32_UART_USART3_DMA_PRIORITY 0 322 #define STM32_UART_UART4_DMA_PRIORITY 0 323 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") 324 325 /* 326 * USB driver system settings. 327 */ 328 #define STM32_USB_USE_USB1 TRUE 329 #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE 330 #define STM32_USB_USB1_HP_IRQ_PRIORITY 5 331 #define STM32_USB_USB1_LP_IRQ_PRIORITY 6 332 333 /* 334 * WDG driver system settings. 335 */ 336 #define STM32_WDG_USE_IWDG FALSE 337 338 #endif /* MCUCONF_H */