mcuconf.h (9928B)
1 /* 2 ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio 3 4 Licensed under the Apache License, Version 2.0 (the "License"); 5 you may not use this file except in compliance with the License. 6 You may obtain a copy of the License at 7 8 http://www.apache.org/licenses/LICENSE-2.0 9 10 Unless required by applicable law or agreed to in writing, software 11 distributed under the License is distributed on an "AS IS" BASIS, 12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 See the License for the specific language governing permissions and 14 limitations under the License. 15 */ 16 17 /* 18 * STM32L4xx drivers configuration. 19 * The following settings override the default settings present in 20 * the various device driver implementation headers. 21 * Note that the settings for each driver only have effect if the whole 22 * driver is enabled in halconf.h. 23 * 24 * IRQ priorities: 25 * 15...0 Lowest...Highest. 26 * 27 * DMA priorities: 28 * 0...3 Lowest...Highest. 29 */ 30 31 #ifndef MCUCONF_H 32 #define MCUCONF_H 33 34 #define STM32L4xx_MCUCONF 35 #define STM32L432_MCUCONF 36 37 /* 38 * HAL driver system settings. 39 */ 40 #define STM32_NO_INIT FALSE 41 #define STM32_VOS STM32_VOS_RANGE1 42 #define STM32_PVD_ENABLE FALSE 43 #define STM32_PLS STM32_PLS_LEV0 44 #define STM32_HSI16_ENABLED TRUE 45 #define STM32_HSI48_ENABLED TRUE 46 #define STM32_LSI_ENABLED FALSE 47 #define STM32_HSE_ENABLED FALSE 48 #define STM32_LSE_ENABLED FALSE 49 #define STM32_MSIPLL_ENABLED FALSE 50 #define STM32_MSIRANGE STM32_MSIRANGE_4M 51 #define STM32_MSISRANGE STM32_MSISRANGE_4M 52 #define STM32_SW STM32_SW_PLL 53 #define STM32_PLLSRC STM32_PLLSRC_HSI16 54 #define STM32_PLLM_VALUE 1 55 #define STM32_PLLN_VALUE 10 56 #define STM32_PLLPDIV_VALUE 0 57 #define STM32_PLLP_VALUE 7 58 #define STM32_PLLQ_VALUE 2 59 #define STM32_PLLR_VALUE 2 60 #define STM32_HPRE STM32_HPRE_DIV1 61 #define STM32_PPRE1 STM32_PPRE1_DIV1 62 #define STM32_PPRE2 STM32_PPRE2_DIV1 63 #define STM32_STOPWUCK STM32_STOPWUCK_MSI 64 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK 65 #define STM32_MCOPRE STM32_MCOPRE_DIV1 66 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK 67 #define STM32_PLLSAI1N_VALUE 24 68 #define STM32_PLLSAI1PDIV_VALUE 0 69 #define STM32_PLLSAI1P_VALUE 7 70 #define STM32_PLLSAI1Q_VALUE 2 71 #define STM32_PLLSAI1R_VALUE 2 72 73 /* 74 * Peripherals clock sources. 75 */ 76 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK 77 #define STM32_USART2SEL STM32_USART2SEL_SYSCLK 78 #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK 79 #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK 80 #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK 81 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 82 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 83 #define STM32_SAI1SEL STM32_SAI1SEL_OFF 84 #define STM32_CLK48SEL STM32_CLK48SEL_HSI48 85 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK 86 #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 87 #define STM32_RTCSEL STM32_RTCSEL_LSI 88 89 /* 90 * IRQ system settings. 91 */ 92 #define STM32_IRQ_EXTI0_PRIORITY 6 93 #define STM32_IRQ_EXTI1_PRIORITY 6 94 #define STM32_IRQ_EXTI2_PRIORITY 6 95 #define STM32_IRQ_EXTI3_PRIORITY 6 96 #define STM32_IRQ_EXTI4_PRIORITY 6 97 #define STM32_IRQ_EXTI5_9_PRIORITY 6 98 #define STM32_IRQ_EXTI10_15_PRIORITY 6 99 #define STM32_IRQ_EXTI1635_38_PRIORITY 6 100 #define STM32_IRQ_EXTI18_PRIORITY 6 101 #define STM32_IRQ_EXTI19_PRIORITY 6 102 #define STM32_IRQ_EXTI20_PRIORITY 6 103 #define STM32_IRQ_EXTI21_22_PRIORITY 15 104 105 #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 106 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 107 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 108 #define STM32_IRQ_TIM1_CC_PRIORITY 7 109 #define STM32_IRQ_TIM2_PRIORITY 7 110 #define STM32_IRQ_TIM6_PRIORITY 7 111 #define STM32_IRQ_TIM7_PRIORITY 7 112 113 #define STM32_IRQ_USART1_PRIORITY 12 114 #define STM32_IRQ_USART2_PRIORITY 12 115 #define STM32_IRQ_LPUART1_PRIORITY 12 116 117 /* 118 * ADC driver system settings. 119 */ 120 #define STM32_ADC_COMPACT_SAMPLES FALSE 121 #define STM32_ADC_USE_ADC1 FALSE 122 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) 123 #define STM32_ADC_ADC1_DMA_PRIORITY 2 124 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 125 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 126 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 127 #define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 128 129 /* 130 * CAN driver system settings. 131 */ 132 #define STM32_CAN_USE_CAN1 FALSE 133 #define STM32_CAN_CAN1_IRQ_PRIORITY 11 134 135 /* 136 * DAC driver system settings. 137 */ 138 #define STM32_DAC_DUAL_MODE FALSE 139 #define STM32_DAC_USE_DAC1_CH1 FALSE 140 #define STM32_DAC_USE_DAC1_CH2 FALSE 141 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 142 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 143 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 144 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 145 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 146 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 147 148 /* 149 * GPT driver system settings. 150 */ 151 #define STM32_GPT_USE_TIM1 FALSE 152 #define STM32_GPT_USE_TIM2 FALSE 153 #define STM32_GPT_USE_TIM6 FALSE 154 #define STM32_GPT_USE_TIM7 FALSE 155 #define STM32_GPT_USE_TIM15 FALSE 156 #define STM32_GPT_USE_TIM16 FALSE 157 158 /* 159 * I2C driver system settings. 160 */ 161 #define STM32_I2C_USE_I2C1 FALSE 162 #define STM32_I2C_USE_I2C3 FALSE 163 #define STM32_I2C_BUSY_TIMEOUT 50 164 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 165 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 166 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 167 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 168 #define STM32_I2C_I2C1_IRQ_PRIORITY 5 169 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 170 #define STM32_I2C_I2C1_DMA_PRIORITY 3 171 #define STM32_I2C_I2C3_DMA_PRIORITY 3 172 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") 173 174 /* 175 * ICU driver system settings. 176 */ 177 #define STM32_ICU_USE_TIM1 FALSE 178 #define STM32_ICU_USE_TIM2 FALSE 179 #define STM32_ICU_USE_TIM15 FALSE 180 #define STM32_ICU_USE_TIM16 FALSE 181 182 /* 183 * PWM driver system settings. 184 */ 185 #define STM32_PWM_USE_TIM1 FALSE 186 #define STM32_PWM_USE_TIM2 FALSE 187 #define STM32_PWM_USE_TIM15 FALSE 188 #define STM32_PWM_USE_TIM16 FALSE 189 190 /* 191 * RTC driver system settings. 192 */ 193 #define STM32_RTC_PRESA_VALUE 32 194 #define STM32_RTC_PRESS_VALUE 1024 195 #define STM32_RTC_CR_INIT 0 196 #define STM32_RTC_TAMPCR_INIT 0 197 198 /* 199 * SERIAL driver system settings. 200 */ 201 #define STM32_SERIAL_USE_USART1 FALSE 202 #define STM32_SERIAL_USE_USART2 FALSE 203 #define STM32_SERIAL_USE_LPUART1 FALSE 204 205 /* 206 * SIO driver system settings. 207 */ 208 #define STM32_SIO_USE_USART1 FALSE 209 #define STM32_SIO_USE_USART2 FALSE 210 #define STM32_SIO_USE_LPUART1 FALSE 211 212 /* 213 * SPI driver system settings. 214 */ 215 #define STM32_SPI_USE_SPI1 FALSE 216 #define STM32_SPI_USE_SPI3 FALSE 217 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) 218 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 219 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) 220 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) 221 #define STM32_SPI_SPI1_DMA_PRIORITY 1 222 #define STM32_SPI_SPI3_DMA_PRIORITY 1 223 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 224 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 225 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") 226 227 /* 228 * ST driver system settings. 229 */ 230 #define STM32_ST_IRQ_PRIORITY 8 231 #define STM32_ST_USE_TIMER 2 232 233 /* 234 * TRNG driver system settings. 235 */ 236 #define STM32_TRNG_USE_RNG1 FALSE 237 238 /* 239 * UART driver system settings. 240 */ 241 #define STM32_UART_USE_USART1 FALSE 242 #define STM32_UART_USE_USART2 FALSE 243 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 244 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) 245 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 246 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 247 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") 248 249 /* 250 * USB driver system settings. 251 */ 252 #define STM32_USB_USE_USB1 TRUE 253 #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE 254 #define STM32_USB_USB1_HP_IRQ_PRIORITY 13 255 #define STM32_USB_USB1_LP_IRQ_PRIORITY 14 256 257 /* 258 * WDG driver system settings. 259 */ 260 #define STM32_WDG_USE_IWDG FALSE 261 262 /* 263 * WSPI driver system settings. 264 */ 265 #define STM32_WSPI_USE_QUADSPI1 FALSE 266 #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 267 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 268 269 #endif /* MCUCONF_H */