mcuconf.h (11358B)
1 /* 2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio 3 Licensed under the Apache License, Version 2.0 (the "License"); 4 you may not use this file except in compliance with the License. 5 You may obtain a copy of the License at 6 http://www.apache.org/licenses/LICENSE-2.0 7 Unless required by applicable law or agreed to in writing, software 8 distributed under the License is distributed on an "AS IS" BASIS, 9 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10 See the License for the specific language governing permissions and 11 limitations under the License. 12 */ 13 14 /* 15 * STM32L4xx drivers configuration. 16 * The following settings override the default settings present in 17 * the various device driver implementation headers. 18 * Note that the settings for each driver only have effect if the whole 19 * driver is enabled in halconf.h. 20 * 21 * IRQ priorities: 22 * 15...0 Lowest...Highest. 23 * 24 * DMA priorities: 25 * 0...3 Lowest...Highest. 26 */ 27 28 #ifndef MCUCONF_H 29 #define MCUCONF_H 30 31 #define STM32L4xx_MCUCONF 32 #define STM32L443_MCUCONF 33 34 /* 35 * HAL driver system settings. 36 */ 37 #define STM32_NO_INIT FALSE 38 #define STM32_VOS STM32_VOS_RANGE1 39 #define STM32_PVD_ENABLE FALSE 40 #define STM32_PLS STM32_PLS_LEV0 41 #define STM32_HSI16_ENABLED TRUE 42 #define STM32_HSI48_ENABLED TRUE 43 #define STM32_LSI_ENABLED FALSE 44 #define STM32_HSE_ENABLED FALSE 45 #define STM32_LSE_ENABLED FALSE 46 #define STM32_MSIPLL_ENABLED FALSE 47 #define STM32_MSIRANGE STM32_MSIRANGE_4M 48 #define STM32_MSISRANGE STM32_MSISRANGE_4M 49 #define STM32_SW STM32_SW_PLL 50 #define STM32_PLLSRC STM32_PLLSRC_HSI16 51 #define STM32_PLLM_VALUE 1 52 #define STM32_PLLN_VALUE 10 53 #define STM32_PLLPDIV_VALUE 0 54 #define STM32_PLLP_VALUE 7 55 #define STM32_PLLQ_VALUE 2 56 #define STM32_PLLR_VALUE 2 57 #define STM32_HPRE STM32_HPRE_DIV1 58 #define STM32_PPRE1 STM32_PPRE1_DIV1 59 #define STM32_PPRE2 STM32_PPRE2_DIV1 60 #define STM32_STOPWUCK STM32_STOPWUCK_MSI 61 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK 62 #define STM32_MCOPRE STM32_MCOPRE_DIV1 63 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK 64 #define STM32_PLLSAI1N_VALUE 24 65 #define STM32_PLLSAI1PDIV_VALUE 0 66 #define STM32_PLLSAI1P_VALUE 7 67 #define STM32_PLLSAI1Q_VALUE 2 68 #define STM32_PLLSAI1R_VALUE 2 69 70 /* 71 * Peripherals clock sources. 72 */ 73 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK 74 #define STM32_USART2SEL STM32_USART2SEL_SYSCLK 75 #define STM32_USART3SEL STM32_USART3SEL_SYSCLK 76 #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK 77 #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK 78 #define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK 79 #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK 80 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 81 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 82 #define STM32_SAI1SEL STM32_SAI1SEL_OFF 83 #define STM32_CLK48SEL STM32_CLK48SEL_HSI48 84 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK 85 #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 86 #define STM32_RTCSEL STM32_RTCSEL_LSI 87 88 /* 89 * IRQ system settings. 90 */ 91 #define STM32_IRQ_EXTI0_PRIORITY 6 92 #define STM32_IRQ_EXTI1_PRIORITY 6 93 #define STM32_IRQ_EXTI2_PRIORITY 6 94 #define STM32_IRQ_EXTI3_PRIORITY 6 95 #define STM32_IRQ_EXTI4_PRIORITY 6 96 #define STM32_IRQ_EXTI5_9_PRIORITY 6 97 #define STM32_IRQ_EXTI10_15_PRIORITY 6 98 #define STM32_IRQ_EXTI1635_38_PRIORITY 6 99 #define STM32_IRQ_EXTI18_PRIORITY 6 100 #define STM32_IRQ_EXTI19_PRIORITY 6 101 #define STM32_IRQ_EXTI20_PRIORITY 6 102 #define STM32_IRQ_EXTI21_22_PRIORITY 15 103 104 #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 105 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 106 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 107 #define STM32_IRQ_TIM1_CC_PRIORITY 7 108 #define STM32_IRQ_TIM2_PRIORITY 7 109 #define STM32_IRQ_TIM6_PRIORITY 7 110 #define STM32_IRQ_TIM7_PRIORITY 7 111 112 #define STM32_IRQ_USART1_PRIORITY 12 113 #define STM32_IRQ_USART2_PRIORITY 12 114 #define STM32_IRQ_USART3_PRIORITY 12 115 #define STM32_IRQ_LPUART1_PRIORITY 12 116 117 /* 118 * ADC driver system settings. 119 */ 120 #define STM32_ADC_COMPACT_SAMPLES FALSE 121 #define STM32_ADC_USE_ADC1 FALSE 122 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) 123 #define STM32_ADC_ADC1_DMA_PRIORITY 2 124 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 125 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 126 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 127 #define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 128 129 /* 130 * CAN driver system settings. 131 */ 132 #define STM32_CAN_USE_CAN1 FALSE 133 #define STM32_CAN_CAN1_IRQ_PRIORITY 11 134 135 /* 136 * DAC driver system settings. 137 */ 138 #define STM32_DAC_DUAL_MODE FALSE 139 #define STM32_DAC_USE_DAC1_CH1 FALSE 140 #define STM32_DAC_USE_DAC1_CH2 FALSE 141 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 142 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 143 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 144 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 145 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 146 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 147 148 /* 149 * GPT driver system settings. 150 */ 151 #define STM32_GPT_USE_TIM1 FALSE 152 #define STM32_GPT_USE_TIM2 FALSE 153 #define STM32_GPT_USE_TIM6 FALSE 154 #define STM32_GPT_USE_TIM7 FALSE 155 #define STM32_GPT_USE_TIM15 FALSE 156 #define STM32_GPT_USE_TIM16 FALSE 157 158 /* 159 * I2C driver system settings. 160 */ 161 #define STM32_I2C_USE_I2C1 FALSE 162 #define STM32_I2C_USE_I2C2 FALSE 163 #define STM32_I2C_USE_I2C3 FALSE 164 #define STM32_I2C_BUSY_TIMEOUT 50 165 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 166 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 167 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) 168 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 169 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 170 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 171 #define STM32_I2C_I2C1_IRQ_PRIORITY 5 172 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 173 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 174 #define STM32_I2C_I2C1_DMA_PRIORITY 3 175 #define STM32_I2C_I2C2_DMA_PRIORITY 3 176 #define STM32_I2C_I2C3_DMA_PRIORITY 3 177 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") 178 179 /* 180 * ICU driver system settings. 181 */ 182 #define STM32_ICU_USE_TIM1 FALSE 183 #define STM32_ICU_USE_TIM2 FALSE 184 #define STM32_ICU_USE_TIM15 FALSE 185 #define STM32_ICU_USE_TIM16 FALSE 186 187 /* 188 * PWM driver system settings. 189 */ 190 #define STM32_PWM_USE_ADVANCED FALSE 191 #define STM32_PWM_USE_TIM1 FALSE 192 #define STM32_PWM_USE_TIM2 FALSE 193 #define STM32_PWM_USE_TIM15 FALSE 194 #define STM32_PWM_USE_TIM16 FALSE 195 196 /* 197 * RTC driver system settings. 198 */ 199 #define STM32_RTC_PRESA_VALUE 32 200 #define STM32_RTC_PRESS_VALUE 1024 201 #define STM32_RTC_CR_INIT 0 202 #define STM32_RTC_TAMPCR_INIT 0 203 204 /* 205 * SDMMC drive system settings. 206 */ 207 #define STM32_SDC_USE_SDMMC1 FALSE 208 #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE 209 #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 210 #define STM32_SDC_SDMMC_READ_TIMEOUT 1000 211 #define STM32_SDC_SDMMC_CLOCK_DELAY 10 212 #define STM32_SDC_SDMMC1_DMA_PRIORITY 3 213 #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 214 #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 215 216 /* 217 * SERIAL driver system settings. 218 */ 219 #define STM32_SERIAL_USE_USART1 FALSE 220 #define STM32_SERIAL_USE_USART2 FALSE 221 #define STM32_SERIAL_USE_USART3 FALSE 222 #define STM32_SERIAL_USE_LPUART1 FALSE 223 #define STM32_SERIAL_USART1_PRIORITY 12 224 #define STM32_SERIAL_USART2_PRIORITY 12 225 #define STM32_SERIAL_USART3_PRIORITY 12 226 #define STM32_SERIAL_LPUART1_PRIORITY 12 227 228 /* 229 * SPI driver system settings. 230 */ 231 #define STM32_SPI_USE_SPI1 FALSE 232 #define STM32_SPI_USE_SPI2 FALSE 233 #define STM32_SPI_USE_SPI3 FALSE 234 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) 235 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) 236 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) 237 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) 238 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) 239 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) 240 #define STM32_SPI_SPI1_DMA_PRIORITY 1 241 #define STM32_SPI_SPI2_DMA_PRIORITY 1 242 #define STM32_SPI_SPI3_DMA_PRIORITY 1 243 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 244 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 245 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 246 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") 247 248 /* 249 * ST driver system settings. 250 */ 251 #define STM32_ST_IRQ_PRIORITY 8 252 #define STM32_ST_USE_TIMER 2 253 254 /* 255 * TRNG driver system settings. 256 */ 257 #define STM32_TRNG_USE_RNG1 FALSE 258 259 /* 260 * UART driver system settings. 261 */ 262 #define STM32_UART_USE_USART1 FALSE 263 #define STM32_UART_USE_USART2 FALSE 264 #define STM32_UART_USE_USART3 FALSE 265 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 266 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) 267 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) 268 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) 269 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) 270 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) 271 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") 272 273 /* 274 * USB driver system settings. 275 */ 276 #define STM32_USB_USE_USB1 TRUE 277 #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE 278 #define STM32_USB_USB1_HP_IRQ_PRIORITY 13 279 #define STM32_USB_USB1_LP_IRQ_PRIORITY 14 280 281 /* 282 * WDG driver system settings. 283 */ 284 #define STM32_WDG_USE_IWDG FALSE 285 286 /* 287 * WSPI driver system settings. 288 */ 289 #define STM32_WSPI_USE_QUADSPI1 FALSE 290 #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) 291 292 #endif /* MCUCONF_H */