qmk_firmware

QMK firmware for my keyboards (Corne, Sweep Ferris) and trackball (Ploopy Adept)
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mcuconf.h (9805B)

      1 /*
      2     ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
      3 
      4     Licensed under the Apache License, Version 2.0 (the "License");
      5     you may not use this file except in compliance with the License.
      6     You may obtain a copy of the License at
      7 
      8         http://www.apache.org/licenses/LICENSE-2.0
      9 
     10     Unless required by applicable law or agreed to in writing, software
     11     distributed under the License is distributed on an "AS IS" BASIS,
     12     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13     See the License for the specific language governing permissions and
     14     limitations under the License.
     15 */
     16 
     17 #ifndef MCUCONF_H
     18 #define MCUCONF_H
     19 
     20 /*
     21  * STM32F4xx drivers configuration.
     22  * The following settings override the default settings present in
     23  * the various device driver implementation headers.
     24  * Note that the settings for each driver only have effect if the whole
     25  * driver is enabled in halconf.h.
     26  *
     27  * IRQ priorities:
     28  * 15...0       Lowest...Highest.
     29  *
     30  * DMA priorities:
     31  * 0...3        Lowest...Highest.
     32  */
     33 
     34 #define STM32F4xx_MCUCONF
     35 #define STM32F411_MCUCONF
     36 
     37 /*
     38  * HAL driver system settings.
     39  */
     40 #define STM32_NO_INIT                       FALSE
     41 #define STM32_PVD_ENABLE                    FALSE
     42 #define STM32_PLS                           STM32_PLS_LEV0
     43 #define STM32_BKPRAM_ENABLE                 FALSE
     44 #define STM32_HSI_ENABLED                   TRUE
     45 #define STM32_LSI_ENABLED                   TRUE
     46 #define STM32_HSE_ENABLED                   TRUE
     47 #define STM32_LSE_ENABLED                   FALSE
     48 #define STM32_CLOCK48_REQUIRED              TRUE
     49 #define STM32_SW                            STM32_SW_PLL
     50 #define STM32_PLLSRC                        STM32_PLLSRC_HSE
     51 #define STM32_PLLM_VALUE                    8
     52 #define STM32_PLLN_VALUE                    336
     53 #define STM32_PLLP_VALUE                    4
     54 #define STM32_PLLQ_VALUE                    7
     55 #define STM32_HPRE                          STM32_HPRE_DIV1
     56 #define STM32_PPRE1                         STM32_PPRE1_DIV2
     57 #define STM32_PPRE2                         STM32_PPRE2_DIV1
     58 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
     59 #define STM32_RTCPRE_VALUE                  8
     60 #define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
     61 #define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
     62 #define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
     63 #define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
     64 #define STM32_I2SSRC                        STM32_I2SSRC_CKIN
     65 #define STM32_PLLI2SN_VALUE                 192
     66 #define STM32_PLLI2SR_VALUE                 5
     67 
     68 /*
     69  * IRQ system settings.
     70  */
     71 #define STM32_IRQ_EXTI0_PRIORITY            6
     72 #define STM32_IRQ_EXTI1_PRIORITY            6
     73 #define STM32_IRQ_EXTI2_PRIORITY            6
     74 #define STM32_IRQ_EXTI3_PRIORITY            6
     75 #define STM32_IRQ_EXTI4_PRIORITY            6
     76 #define STM32_IRQ_EXTI5_9_PRIORITY          6
     77 #define STM32_IRQ_EXTI10_15_PRIORITY        6
     78 #define STM32_IRQ_EXTI16_PRIORITY           6
     79 #define STM32_IRQ_EXTI17_PRIORITY           15
     80 #define STM32_IRQ_EXTI18_PRIORITY           6
     81 #define STM32_IRQ_EXTI19_PRIORITY           6
     82 #define STM32_IRQ_EXTI20_PRIORITY           6
     83 #define STM32_IRQ_EXTI21_PRIORITY           15
     84 #define STM32_IRQ_EXTI22_PRIORITY           15
     85 
     86 #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY    7
     87 #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY    7
     88 #define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
     89 #define STM32_IRQ_TIM1_CC_PRIORITY          7
     90 #define STM32_IRQ_TIM2_PRIORITY             7
     91 #define STM32_IRQ_TIM3_PRIORITY             7
     92 #define STM32_IRQ_TIM4_PRIORITY             7
     93 #define STM32_IRQ_TIM5_PRIORITY             7
     94 
     95 #define STM32_IRQ_USART1_PRIORITY           12
     96 #define STM32_IRQ_USART2_PRIORITY           12
     97 #define STM32_IRQ_USART6_PRIORITY           12
     98 
     99 /*
    100  * ADC driver system settings.
    101  */
    102 #define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
    103 #define STM32_ADC_USE_ADC1                  FALSE
    104 #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
    105 #define STM32_ADC_ADC1_DMA_PRIORITY         2
    106 #define STM32_ADC_IRQ_PRIORITY              6
    107 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
    108 
    109 /*
    110  * GPT driver system settings.
    111  */
    112 #define STM32_GPT_USE_TIM1                  FALSE
    113 #define STM32_GPT_USE_TIM2                  FALSE
    114 #define STM32_GPT_USE_TIM3                  FALSE
    115 #define STM32_GPT_USE_TIM4                  FALSE
    116 #define STM32_GPT_USE_TIM5                  FALSE
    117 #define STM32_GPT_USE_TIM9                  FALSE
    118 #define STM32_GPT_USE_TIM10                 FALSE
    119 #define STM32_GPT_USE_TIM11                 FALSE
    120 
    121 /*
    122  * I2C driver system settings.
    123  */
    124 #define STM32_I2C_USE_I2C1                  TRUE
    125 #define STM32_I2C_USE_I2C2                  FALSE
    126 #define STM32_I2C_USE_I2C3                  FALSE
    127 #define STM32_I2C_BUSY_TIMEOUT              50
    128 #define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
    129 #define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
    130 #define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
    131 #define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
    132 #define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
    133 #define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
    134 #define STM32_I2C_I2C1_IRQ_PRIORITY         5
    135 #define STM32_I2C_I2C2_IRQ_PRIORITY         5
    136 #define STM32_I2C_I2C3_IRQ_PRIORITY         5
    137 #define STM32_I2C_I2C1_DMA_PRIORITY         3
    138 #define STM32_I2C_I2C2_DMA_PRIORITY         3
    139 #define STM32_I2C_I2C3_DMA_PRIORITY         3
    140 #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
    141 
    142 /*
    143  * I2S driver system settings.
    144  */
    145 #define STM32_I2S_USE_SPI2                  FALSE
    146 #define STM32_I2S_USE_SPI3                  FALSE
    147 #define STM32_I2S_SPI2_IRQ_PRIORITY         10
    148 #define STM32_I2S_SPI3_IRQ_PRIORITY         10
    149 #define STM32_I2S_SPI2_DMA_PRIORITY         1
    150 #define STM32_I2S_SPI3_DMA_PRIORITY         1
    151 #define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
    152 #define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
    153 #define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
    154 #define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
    155 #define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
    156 
    157 /*
    158  * ICU driver system settings.
    159  */
    160 #define STM32_ICU_USE_TIM1                  FALSE
    161 #define STM32_ICU_USE_TIM2                  FALSE
    162 #define STM32_ICU_USE_TIM3                  FALSE
    163 #define STM32_ICU_USE_TIM4                  FALSE
    164 #define STM32_ICU_USE_TIM5                  FALSE
    165 #define STM32_ICU_USE_TIM9                  FALSE
    166 #define STM32_ICU_USE_TIM10                 FALSE
    167 #define STM32_ICU_USE_TIM11                 FALSE
    168 
    169 /*
    170  * PWM driver system settings.
    171  */
    172 #define STM32_PWM_USE_TIM1                  FALSE
    173 #define STM32_PWM_USE_TIM2                  FALSE
    174 #define STM32_PWM_USE_TIM3                  FALSE
    175 #define STM32_PWM_USE_TIM4                  FALSE
    176 #define STM32_PWM_USE_TIM5                  FALSE
    177 #define STM32_PWM_USE_TIM9                  FALSE
    178 #define STM32_PWM_USE_TIM10                 FALSE
    179 #define STM32_PWM_USE_TIM11                 FALSE
    180 
    181 /*
    182  * RTC driver system settings.
    183  */
    184 #define STM32_RTC_PRESA_VALUE               32
    185 #define STM32_RTC_PRESS_VALUE               1024
    186 #define STM32_RTC_CR_INIT                   0
    187 #define STM32_RTC_TAMPCR_INIT               0
    188 
    189 /*
    190  * SERIAL driver system settings.
    191  */
    192 #define STM32_SERIAL_USE_USART1             TRUE
    193 #define STM32_SERIAL_USE_USART2             TRUE
    194 #define STM32_SERIAL_USE_USART6             FALSE
    195 
    196 /*
    197  * SPI driver system settings.
    198  */
    199 #define STM32_SPI_USE_SPI1                  TRUE
    200 #define STM32_SPI_USE_SPI2                  FALSE
    201 #define STM32_SPI_USE_SPI3                  FALSE
    202 #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
    203 #define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
    204 #define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
    205 #define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
    206 #define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
    207 #define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
    208 #define STM32_SPI_SPI1_DMA_PRIORITY         1
    209 #define STM32_SPI_SPI2_DMA_PRIORITY         1
    210 #define STM32_SPI_SPI3_DMA_PRIORITY         1
    211 #define STM32_SPI_SPI1_IRQ_PRIORITY         10
    212 #define STM32_SPI_SPI2_IRQ_PRIORITY         10
    213 #define STM32_SPI_SPI3_IRQ_PRIORITY         10
    214 #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
    215 
    216 /*
    217  * ST driver system settings.
    218  */
    219 #define STM32_ST_IRQ_PRIORITY               8
    220 #define STM32_ST_USE_TIMER                  2
    221 
    222 /*
    223  * UART driver system settings.
    224  */
    225 #define STM32_UART_USE_USART1               FALSE
    226 #define STM32_UART_USE_USART2               FALSE
    227 #define STM32_UART_USE_USART6               FALSE
    228 #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
    229 #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
    230 #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
    231 #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
    232 #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
    233 #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
    234 #define STM32_UART_USART1_DMA_PRIORITY      0
    235 #define STM32_UART_USART2_DMA_PRIORITY      0
    236 #define STM32_UART_USART6_DMA_PRIORITY      0
    237 #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
    238 
    239 /*
    240  * USB driver system settings.
    241  */
    242 #define STM32_USB_USE_OTG1                  TRUE
    243 #define STM32_USB_OTG1_IRQ_PRIORITY         14
    244 #define STM32_USB_OTG1_RX_FIFO_SIZE         512
    245 #define STM32_USB_HOST_WAKEUP_DURATION      2
    246 
    247 /*
    248  * WDG driver system settings.
    249  */
    250 #define STM32_WDG_USE_IWDG                  FALSE
    251 
    252 #endif /* MCUCONF_H */