rv32g-core, branch HEAD

update README with current milestone

2026-08-21T23:46:35Z

commit 7265302587f4476b0746d5f3a682f4108b284ae4 parent 96ed6dba8e30b9ae0fc2758d6ac7fd7ff59d56ba Author: Vineet Kumar Date: Sat, 22 Aug 2026 05:16:35 +0530 update README with current milestone I unfortunately could not work on this as much as I'd have liked over this summer :( Recovery-Origin: 9433c749371ec6e67e38404e4735f101da1fa9e3 Recovery-Status: reconstructed history Complete final source tree is exact: every path, mode and blob matches original August22 tree dc03c2fb4d5e24ec4aedb7c18b8889b7bb2769a4. Original parent history is reconstructed, so this new commit has a different ID.

remove addi to nop decoding because of comparison

2026-08-21T23:31:32Z

commit 96ed6dba8e30b9ae0fc2758d6ac7fd7ff59d56ba parent 8ff59035f7ac85e58ee138217a3d3674e38d8d6b Author: Vineet Kumar Date: Sat, 22 Aug 2026 05:01:32 +0530 remove addi to nop decoding because of comparison Recovery-Origin: e55684bbb758547c693fabd693e1e8bdd122542a Recovery-Status: reconstructed history Removed the reconstructed explicit ADDI-as-NOP special case, reaching the hash-verified final stage_decode.sv. Original intermediate commit object is missing.

remove expensive redundant name-based opcode decoding

2026-08-21T22:55:40Z

commit 8ff59035f7ac85e58ee138217a3d3674e38d8d6b parent 56f88f259a5816f0990835871442c477c73c251d Author: Vineet Kumar Date: Sat, 22 Aug 2026 04:25:40 +0530 remove expensive redundant name-based opcode decoding Recovery-Origin: e0d56cb9dad1438e5645bfbb464f2ab287696347 Recovery-Status: reconstructed history Reconstructed direct opcode/funct3 control decoding and removed unused instruction-name enum and PC passthrough. Final hart/pkg/decoder are hash-verified originals; the temporary explicit ADDI-as-NOP block is an inferred intermediate state for the following documented removal.

split memop into loadop and storeop

2026-08-11T11:40:44Z

commit 56f88f259a5816f0990835871442c477c73c251d parent dc8fcb6a7c3a5c649e07501dfd5b125ad2c301d6 Author: Vineet Kumar Date: Tue, 11 Aug 2026 17:10:44 +0530 split memop into loadop and storeop Recovery-Origin: 7865eed346008c19d94bb6963010a9b24244028d Recovery-Status: reconstructed history Reconstructed split load/store control types, memory-stage interface and testbench from intact Aug22 pre-amendment RTL. Intermediate Aug11/Aug18 source is unavailable; exact attribution of individual edits is uncertain.

import riscv-tests' license and readme file

2026-08-09T11:24:33Z

commit dc8fcb6a7c3a5c649e07501dfd5b125ad2c301d6 parent bc45a18510474069f97c55481f64f2397ba69444 Author: Vineet Kumar Date: Sun, 9 Aug 2026 16:54:33 +0530 import riscv-tests' license and readme file I forgot to place it when I vendored the tests. felt wrong to ignore it once I noticed since it's differently licensed. Recovery-Origin: 5f4319bd2332b8d99c615a5ecbddcc2052bd2033 Recovery-Status: reconstructed history Restored the surviving vendored riscv-tests license/readme additions. Original root README and RTL subtree are missing; retain the previous versions rather than invent undocumented edits.

fold i-cache tag+valid into BSRAM to cut critical path

2026-08-07T09:10:04Z

commit bc45a18510474069f97c55481f64f2397ba69444 parent 6a78ab80cc3de152aca15c5dcf416ba2c3cb3c6a Author: Vineet Kumar Date: Fri, 7 Aug 2026 14:40:04 +0530 fold i-cache tag+valid into BSRAM to cut critical path Recovery-Origin: a139678b4ed4a1ad5293bc95b89fa6527b24b669 Recovery-Status: reconstructed history Recovered final stage_fetch.sv supplies combined tag/valid block-RAM storage and sweep invalidation. Assigning this surviving file to this commit follows its reflog message; the original commit object is missing.

increase cache_size to 2K words from 256 to better use BSRAM

2026-08-07T07:01:13Z

commit 6a78ab80cc3de152aca15c5dcf416ba2c3cb3c6a parent 3b842277ef7a42858e7de7cd9fc8dca5800753a0 Author: Vineet Kumar Date: Fri, 7 Aug 2026 12:31:13 +0530 increase cache_size to 2K words from 256 to better use BSRAM Recovery-Origin: e9130fb4b9c4d689af6886ff9fa73b5aa19eebb6 Recovery-Status: reconstructed history Reimplemented the one-line cache-size change from its reflog message and intact before/after source.

reduce pipeline critical path delay

2026-08-06T17:32:33Z

commit 3b842277ef7a42858e7de7cd9fc8dca5800753a0 parent 57f97ea9a2d53e0e618a00e05e2eb24a5fc10c6b Author: Vineet Kumar Date: Thu, 6 Aug 2026 23:02:33 +0530 reduce pipeline critical path delay Recovery-Origin: 4373f2fe41311b37aaf19ddc05a57f7e55661cb0 Recovery-Status: reconstructed history Reconstructed from intact earlier amendment 75f524f and later surviving RTL: preserve pipeline optimization, registered PC+4 and pipeline reset changes. Exact final amendment object is missing; allocation of later observed changes to this commit is inferred.

fix pipeline by handling hazards, aligning data-memory, and registered reads

2026-08-06T15:47:51Z

commit 57f97ea9a2d53e0e618a00e05e2eb24a5fc10c6b parent 0b72748e55a5126780ae81c30ef9b3509c54ff93 Author: Vineet Kumar Date: Thu, 6 Aug 2026 21:17:51 +0530 fix pipeline by handling hazards, aligning data-memory, and registered reads

remove the unused result address from test cases

2026-08-06T13:25:45Z

commit 0b72748e55a5126780ae81c30ef9b3509c54ff93 parent 4c660e7b7a14192c296f37bb5fab00f011e1d559 Author: Vineet Kumar Date: Thu, 6 Aug 2026 18:55:45 +0530 remove the unused result address from test cases just printing the register directly like I'm doing right now is easier while in simulation.

print the unmodified failed test number

2026-08-05T09:12:55Z

commit 4c660e7b7a14192c296f37bb5fab00f011e1d559 parent 496803058d353510bac07fdb87673442e4298934 Author: Vineet Kumar Date: Wed, 5 Aug 2026 14:42:55 +0530 print the unmodified failed test number

test only for rv32ui right now

2026-08-05T09:12:41Z

commit 496803058d353510bac07fdb87673442e4298934 parent 7dc30f86975ae4540c0449692d7efb4ef62005a3 Author: Vineet Kumar Date: Wed, 5 Aug 2026 14:42:41 +0530 test only for rv32ui right now

fix test running and remove rv64-specific tests

2026-08-04T12:42:36Z

commit 7dc30f86975ae4540c0449692d7efb4ef62005a3 parent fe9f4859cde2e57a482a8af26275e659bcf6f6c7 Author: Vineet Kumar Date: Tue, 4 Aug 2026 18:12:36 +0530 fix test running and remove rv64-specific tests

vendor riscv-tests with using result address instead of zicsr

2026-08-04T10:11:02Z

commit fe9f4859cde2e57a482a8af26275e659bcf6f6c7 parent 26ae3798b9234e981551a99392e5dcd1ada184bf Author: Vineet Kumar Date: Tue, 4 Aug 2026 15:41:02 +0530 vendor riscv-tests with using result address instead of zicsr also makes it easy for me to find out if a test actually finished instead of inferring based on PC

remove github:riscv-software-src/riscv-tests submodule

2026-08-04T10:02:00Z

commit 26ae3798b9234e981551a99392e5dcd1ada184bf parent 10f35c6bdf802e170ba5dfa529cb8d1665af7784 Author: Vineet Kumar Date: Tue, 4 Aug 2026 15:32:00 +0530 remove github:riscv-software-src/riscv-tests submodule

pipeline register reset's pc should use BASE_ADDR const

2026-07-26T10:57:33Z

commit 10f35c6bdf802e170ba5dfa529cb8d1665af7784 parent 9923ef798058d98b7ac10e83812c8081abdc465a Author: Vineet Kumar Date: Sun, 26 Jul 2026 16:27:33 +0530 pipeline register reset's pc should use BASE_ADDR const

fix wrong pipeline register being used in next_pc calculation

2026-07-26T10:57:19Z

commit 9923ef798058d98b7ac10e83812c8081abdc465a parent ad9c2331c5cac454638c37f5cfaa7a8e21fe5636 Author: Vineet Kumar Date: Sun, 26 Jul 2026 16:27:19 +0530 fix wrong pipeline register being used in next_pc calculation

stop using I-cache until I fix pipelining

2026-07-26T10:56:42Z

commit ad9c2331c5cac454638c37f5cfaa7a8e21fe5636 parent cc90ca030e0a259c08c3594e8863a84ff8f3837b Author: Vineet Kumar Date: Sun, 26 Jul 2026 16:26:42 +0530 stop using I-cache until I fix pipelining

exit sim on a 32'b0 after any real inst

2026-07-26T10:56:14Z

commit cc90ca030e0a259c08c3594e8863a84ff8f3837b parent ee09c9c5256dc0acdda766cd402000535e7ee169 Author: Vineet Kumar Date: Sun, 26 Jul 2026 16:26:14 +0530 exit sim on a 32'b0 after any real inst

remove erroneous basic pipelining complete mention in readme

2026-07-24T08:44:17Z

commit ee09c9c5256dc0acdda766cd402000535e7ee169 parent 3f985ccdd3b60c810fa0cd95a62f990cdbbef21c Author: Vineet Kumar Date: Fri, 24 Jul 2026 14:14:17 +0530 remove erroneous basic pipelining complete mention in readme It's not done yet, it still has errors that need to be ironed out.

switch pipeline registers to sync reset

2026-07-24T08:44:08Z

commit 3f985ccdd3b60c810fa0cd95a62f990cdbbef21c parent 9ac7b30411ff32d47929d3a33f070f2c46696589 Author: Vineet Kumar Date: Fri, 24 Jul 2026 14:14:08 +0530 switch pipeline registers to sync reset

remove zicsr extension for now due to issues

2026-07-24T08:17:51Z

commit 9ac7b30411ff32d47929d3a33f070f2c46696589 parent bc62a1834a9e97d3efbab4ac384379738544b6d9 Author: Vineet Kumar Date: Fri, 24 Jul 2026 13:47:51 +0530 remove zicsr extension for now due to issues 1. It was interfering with the pipelining of the hart like hazards. 2. CSRs take up lots of BRAM that I could've put towards more I-cache/D-cache. 3. I wasn't planning on using an existing OS/EEI like Linux/FreeRTOS, instead wanting to make my own. 4. Parts of it was initially LLM slop. I'd rather revisit this once I got most of the other more important major extensions completed as I see those to be much more useful.

move $display() messages to tb

2026-07-14T07:59:40Z

commit bc62a1834a9e97d3efbab4ac384379738544b6d9 parent a27f857278de6f860ba720e069848f206e54bd43 Author: Vineet Kumar Date: Tue, 14 Jul 2026 13:29:40 +0530 move $display() messages to tb

properly latch the pipeline registers

2026-07-14T07:56:21Z

commit a27f857278de6f860ba720e069848f206e54bd43 parent 56b8baf09f4372bae891e08a3a93fff1741fe48c Author: Vineet Kumar Date: Tue, 14 Jul 2026 13:26:21 +0530 properly latch the pipeline registers

remove tb prematurely exiting on ecall/ebreak

2026-07-13T04:42:55Z

commit 56b8baf09f4372bae891e08a3a93fff1741fe48c parent 55ea46312b825c0c2c238bb14f6c853a334c6a3e Author: Vineet Kumar Date: Mon, 13 Jul 2026 10:12:55 +0530 remove tb prematurely exiting on ecall/ebreak

insert stall after csr regfile registered read

2026-07-13T04:42:00Z

commit 55ea46312b825c0c2c238bb14f6c853a334c6a3e parent 6d5c2288a6e946986faf1f57f0355c30c1b0c6b8 Author: Vineet Kumar Date: Mon, 13 Jul 2026 10:12:00 +0530 insert stall after csr regfile registered read

optimize csr address decoding from priv spec 2.1

2026-07-12T15:40:51Z

commit 6d5c2288a6e946986faf1f57f0355c30c1b0c6b8 parent 4d57607f9897c3f96812d96bae95427f3f24d361 Author: Vineet Kumar Date: Sun, 12 Jul 2026 21:10:51 +0530 optimize csr address decoding from priv spec 2.1

fix readme's claim about zicsr+mret having identical performance and usage

2026-07-12T09:35:11Z

commit 4d57607f9897c3f96812d96bae95427f3f24d361 parent b2f619d2772cb7e6a9f951d15cd6d4fda3b27f76 Author: Vineet Kumar Date: Sun, 12 Jul 2026 15:05:11 +0530 fix readme's claim about zicsr+mret having identical performance and usage

fix csr regfile memory inference

2026-07-12T06:46:23Z

commit b2f619d2772cb7e6a9f951d15cd6d4fda3b27f76 parent e47093efc32ef69a2bdc66a837d437e1958bd158 Author: Vineet Kumar Date: Sun, 12 Jul 2026 12:16:23 +0530 fix csr regfile memory inference

make unified memory have registered reads again

2026-07-11T13:00:16Z

commit e47093efc32ef69a2bdc66a837d437e1958bd158 parent 364ec7627b3932d642f2b4bf813b7493e721ed1e Author: Vineet Kumar Date: Sat, 11 Jul 2026 18:30:16 +0530 make unified memory have registered reads again

fix synth errors

2026-07-11T13:00:05Z

commit 364ec7627b3932d642f2b4bf813b7493e721ed1e parent a5c4877aa2e01078002f5d1d3ed3fbe73578e005 Author: Vineet Kumar Date: Sat, 11 Jul 2026 18:30:05 +0530 fix synth errors

make pnr make target depend on synth

2026-07-11T12:46:03Z

commit a5c4877aa2e01078002f5d1d3ed3fbe73578e005 parent e430c49fa9aa74e23e9aaea96bb9a88ede26115b Author: Vineet Kumar Date: Sat, 11 Jul 2026 18:16:03 +0530 make pnr make target depend on synth

ignore rom.txt in .gitignore

2026-07-11T09:26:15Z

commit e430c49fa9aa74e23e9aaea96bb9a88ede26115b parent 8b56d0a6a6b0256eff987ce8fa89a176d9fc6738 Author: Vineet Kumar Date: Sat, 11 Jul 2026 14:56:15 +0530 ignore rom.txt in .gitignore

do initial pipelining

2026-07-11T09:25:42Z

commit 8b56d0a6a6b0256eff987ce8fa89a176d9fc6738 parent 78d9f04bd0c4aa9e4853d1fa336d4064b3ad2f91 Author: Vineet Kumar Date: Sat, 11 Jul 2026 14:55:42 +0530 do initial pipelining

implement privileged MRET instruction

2026-07-08T09:41:42Z

commit 78d9f04bd0c4aa9e4853d1fa336d4064b3ad2f91 parent 452fc47fa674c4c686416465b9c939568df910fa Author: Vineet Kumar Date: Wed, 8 Jul 2026 15:11:42 +0530 implement privileged MRET instruction

stop simulation when illegal instruction encountered

2026-07-06T12:10:51Z

commit 452fc47fa674c4c686416465b9c939568df910fa parent b1da71976298dbebb4c5acef8b37d2973d44e47a Author: Vineet Kumar Date: Mon, 6 Jul 2026 17:40:51 +0530 stop simulation when illegal instruction encountered

implement Zicsr

2026-07-06T12:10:39Z

commit b1da71976298dbebb4c5acef8b37d2973d44e47a parent 564723b1aa15d081506e9ebba9c05fd5a9da6296 Author: Vineet Kumar Date: Mon, 6 Jul 2026 17:40:39 +0530 implement Zicsr

exit simulation on EXC_ILL_INST again

2026-07-03T15:49:15Z

commit 564723b1aa15d081506e9ebba9c05fd5a9da6296 parent f75f946e047adfd2344e183e6f2b4f31ea153180 Author: Vineet Kumar Date: Fri, 3 Jul 2026 21:19:15 +0530 exit simulation on EXC_ILL_INST again

increase icache depth to 8K words

2026-06-18T20:58:45Z

commit f75f946e047adfd2344e183e6f2b4f31ea153180 parent ff697575ef55ed75410e7966dd0db8e57b073162 Author: Vineet Kumar Date: Thu, 18 Jun 2026 16:58:45 -0400 increase icache depth to 8K words

update readme with current progress

2026-06-12T04:42:02Z

commit ff697575ef55ed75410e7966dd0db8e57b073162 parent 419dcb72107c7fcea7695bed6d722bc8a6921b44 Author: Vineet Kumar Date: Fri, 12 Jun 2026 00:42:02 -0400 update readme with current progress

add librelane

2026-06-12T04:41:13Z

commit 419dcb72107c7fcea7695bed6d722bc8a6921b44 parent 84f8e967e9967417469d344beba129e4d2cc21aa Author: Vineet Kumar Date: Fri, 12 Jun 2026 00:41:13 -0400 add librelane

make it easy to enable/disable i-cache when fetching (synth-time)

2026-06-11T20:52:42Z

commit 84f8e967e9967417469d344beba129e4d2cc21aa parent c0570886bd05ba4405a31e00b4140b46150202e1 Author: Vineet Kumar Date: Thu, 11 Jun 2026 16:52:42 -0400 make it easy to enable/disable i-cache when fetching (synth-time)

temporarily decrease cache depth to 64 words

2026-06-11T01:20:54Z

commit c0570886bd05ba4405a31e00b4140b46150202e1 parent d9c131d821c269835722e634cf8dca7529f811dc Author: Vineet Kumar Date: Wed, 10 Jun 2026 21:20:54 -0400 temporarily decrease cache depth to 64 words

add pnr makefile target

2026-06-11T01:11:00Z

commit d9c131d821c269835722e634cf8dca7529f811dc parent 5f15f69a4fa7550162b0f666e55801e102168c3d Author: Vineet Kumar Date: Wed, 10 Jun 2026 21:11:00 -0400 add pnr makefile target

comment out unused async resets in hart to remove comb. rst LUTs

2026-06-11T00:45:38Z

commit 5f15f69a4fa7550162b0f666e55801e102168c3d parent 7bf7051954fa3b626c579b331b72f0078c6c8691 Author: Vineet Kumar Date: Wed, 10 Jun 2026 20:45:38 -0400 comment out unused async resets in hart to remove comb. rst LUTs this reduced LUTs by nearly 4k and also increased fmax to 19 (from 17) and 29 (from 25) MHz for a nice +15% boost by just doing tihs.

make fpga temp. top module and add dmem_valid output to unified_memory

2026-06-11T00:44:38Z

commit 7bf7051954fa3b626c579b331b72f0078c6c8691 parent 79c6c61d54ef8b96ed8395845ac1d08e84f9c304 Author: Vineet Kumar Date: Wed, 10 Jun 2026 20:44:38 -0400 make fpga temp. top module and add dmem_valid output to unified_memory currently getting in nextpnr 17 MHz (before routing optimization?) and then ~25 MHz (after its auto-optimization?)

check if pass and fail functions exist in test, print if not

2026-06-10T18:41:44Z

commit 79c6c61d54ef8b96ed8395845ac1d08e84f9c304 parent f48d239dd38f14746d5a9affcc4cb5122e692eeb Author: Vineet Kumar Date: Wed, 10 Jun 2026 14:41:44 -0400 check if pass and fail functions exist in test, print if not

fix shamt to be combinational assign, not initial

2026-06-10T00:20:00Z

commit f48d239dd38f14746d5a9affcc4cb5122e692eeb parent dce248adc7f59090c3035d6d395da4c0f9bbef72 Author: Vineet Kumar Date: Tue, 9 Jun 2026 20:20:00 -0400 fix shamt to be combinational assign, not initial same logic error as a previous commit for a different instruction

write data memory according to the byte location

2026-06-09T23:01:06Z

commit dce248adc7f59090c3035d6d395da4c0f9bbef72 parent ca88f5c5782dfc55a075fdff71544eb389da85f8 Author: Vineet Kumar Date: Tue, 9 Jun 2026 19:01:06 -0400 write data memory according to the byte location

try fixing the icache's aliasing

2026-06-09T22:44:39Z

commit ca88f5c5782dfc55a075fdff71544eb389da85f8 parent 1384860501c9f2aa08e81a6a7754614107877ac8 Author: Vineet Kumar Date: Tue, 9 Jun 2026 18:44:39 -0400 try fixing the icache's aliasing

implement better testing infrastructure

2026-06-09T22:44:22Z

commit 1384860501c9f2aa08e81a6a7754614107877ac8 parent 6e3e57beecc47d358c5706f7eef0efc2ee64ea3d Author: Vineet Kumar Date: Tue, 9 Jun 2026 18:44:22 -0400 implement better testing infrastructure

move unified memory read to be combinational for single-cycle

2026-06-09T18:45:23Z

commit 6e3e57beecc47d358c5706f7eef0efc2ee64ea3d parent dafb90c3fb697598b3c8972cc5602b5ffa24228b Author: Vineet Kumar Date: Tue, 9 Jun 2026 14:45:23 -0400 move unified memory read to be combinational for single-cycle otherwise doing registered read on single-cycle instead of pipelined causes rv32ui-p-fence_i to fail

change finish condition of testbench to include '0 inst

2026-06-09T18:45:00Z

commit dafb90c3fb697598b3c8972cc5602b5ffa24228b parent 57387869f290867fc0691098e3d1633c18c8bd17 Author: Vineet Kumar Date: Tue, 9 Jun 2026 14:45:00 -0400 change finish condition of testbench to include '0 inst

implement a sort of modified harvard arch. and icache flushing

2026-06-09T04:31:42Z

commit 57387869f290867fc0691098e3d1633c18c8bd17 parent 0ebcccf55db0716499c5c2f259694a3544d773b7 Author: Vineet Kumar Date: Tue, 9 Jun 2026 00:31:42 -0400 implement a sort of modified harvard arch. and icache flushing needed to pass the rv32ui-p-fence_i test. it seems to require supporting self-modifying programs, which the previous way did not allow.

update makefile

2026-06-09T04:29:45Z

commit 0ebcccf55db0716499c5c2f259694a3544d773b7 parent 6d2ce6f3c127bac56ba7f49f15cfe7049f2626f1 Author: Vineet Kumar Date: Tue, 9 Jun 2026 00:29:45 -0400 update makefile

implement Zifencei as a nop

2026-06-08T21:45:08Z

commit 6d2ce6f3c127bac56ba7f49f15cfe7049f2626f1 parent 34a120d7b08431486d84157a8922e6856af50405 Author: Vineet Kumar Date: Mon, 8 Jun 2026 17:45:08 -0400 implement Zifencei as a nop

add rv32 toolchain to manifest.scm

2026-06-08T21:40:34Z

commit 34a120d7b08431486d84157a8922e6856af50405 parent 32fe040d304c97cd13c82b9cd44e1fe5a0082245 Author: Vineet Kumar Date: Mon, 8 Jun 2026 17:40:34 -0400 add rv32 toolchain to manifest.scm

increase tb imem to 1K and dmem to 4K

2026-06-08T20:14:53Z

commit 32fe040d304c97cd13c82b9cd44e1fe5a0082245 parent f9320e371da369ef1b75e072dee542f86c6c12f4 Author: Vineet Kumar Date: Mon, 8 Jun 2026 16:14:53 -0400 increase tb imem to 1K and dmem to 4K

remove the temporary inst opcode decoding debug message

2026-06-08T20:14:24Z

commit f9320e371da369ef1b75e072dee542f86c6c12f4 parent 34a9291bb58c54a908fd48f3f69abc9fd5ff62d6 Author: Vineet Kumar Date: Mon, 8 Jun 2026 16:14:24 -0400 remove the temporary inst opcode decoding debug message

fix faulty nop detection in decoding

2026-06-08T19:07:18Z

commit 34a9291bb58c54a908fd48f3f69abc9fd5ff62d6 parent 97385bda2d364514abda2a3df050a2122a88d572 Author: Vineet Kumar Date: Mon, 8 Jun 2026 15:07:18 -0400 fix faulty nop detection in decoding this caused rv32ui-p-addi test to fail previously

fix instruction decoding in decoding logic to not use initial assignment

2026-06-08T18:53:46Z

commit 97385bda2d364514abda2a3df050a2122a88d572 parent 43a3c59161d6e8f700143d96eae06e25bd830f99 Author: Vineet Kumar Date: Mon, 8 Jun 2026 14:53:46 -0400 fix instruction decoding in decoding logic to not use initial assignment basically what it seemed to previously do was it stayed on the first instruction and never updated afterward since it wasn't in a combinational block

update rom.txt to be rv32ui-p-addi and increase rom size to 1024 words

2026-06-08T18:53:07Z

commit 43a3c59161d6e8f700143d96eae06e25bd830f99 parent e8a42ce6ad99bde0c0194a25f4dcc33d94de1895 Author: Vineet Kumar Date: Mon, 8 Jun 2026 14:53:07 -0400 update rom.txt to be rv32ui-p-addi and increase rom size to 1024 words

output better logging

2026-06-08T18:52:58Z

commit e8a42ce6ad99bde0c0194a25f4dcc33d94de1895 parent dd1ae9ee4aa0872f82646e895d2a79df07cdff8d Author: Vineet Kumar Date: Mon, 8 Jun 2026 14:52:58 -0400 output better logging

print current cycle

2026-06-07T22:57:34Z

commit dd1ae9ee4aa0872f82646e895d2a79df07cdff8d parent 882db63ddf63461fedb7bbfc77c3b0f385a858bc Author: Vineet Kumar Date: Sun, 7 Jun 2026 18:57:34 -0400 print current cycle

add very basic testbench

2026-06-07T21:56:11Z

commit 882db63ddf63461fedb7bbfc77c3b0f385a858bc parent 95b479231c2f5959608a338830ef10baa65446f7 Author: Vineet Kumar Date: Sun, 7 Jun 2026 17:56:11 -0400 add very basic testbench

replace casez with case inside

2026-06-04T22:33:22Z

commit 95b479231c2f5959608a338830ef10baa65446f7 parent da699fe51c52c7d42d4ed55683d322115117b376 Author: Vineet Kumar Date: Thu, 4 Jun 2026 18:33:22 -0400 replace casez with case inside apparently latter replaced former in systemverilog

add resources and LLM disclosure to README

2026-06-03T20:06:36Z

commit da699fe51c52c7d42d4ed55683d322115117b376 parent 4bef323217454349b806321de1a4fb30a4374b13 Author: Vineet Kumar Date: Wed, 3 Jun 2026 16:06:36 -0400 add resources and LLM disclosure to README

use gowin-specific synthesis flow

2026-06-03T17:19:14Z

commit 4bef323217454349b806321de1a4fb30a4374b13 parent 46faf7ecf266867f88dc1b231b59218b96ceabaa Author: Vineet Kumar Date: Wed, 3 Jun 2026 13:19:14 -0400 use gowin-specific synthesis flow

add makefile for linting and synthesis

2026-06-03T02:03:32Z

commit 46faf7ecf266867f88dc1b231b59218b96ceabaa parent 752f85caec05a75087f8dec4e2cdab4935ae3661 Author: Vineet Kumar Date: Tue, 2 Jun 2026 22:03:32 -0400 add makefile for linting and synthesis

fix synthesis issues

2026-06-03T01:54:39Z

commit 752f85caec05a75087f8dec4e2cdab4935ae3661 parent 6f52fe98d857ebe9298a5cf2dbd729f6c129247b Author: Vineet Kumar Date: Tue, 2 Jun 2026 21:54:39 -0400 fix synthesis issues

add .gitignore

2026-06-02T18:58:48Z

commit 6f52fe98d857ebe9298a5cf2dbd729f6c129247b parent 43306a63fb75f3320de54b7909f6d2003cd1872a Author: Vineet Kumar Date: Tue, 2 Jun 2026 14:58:48 -0400 add .gitignore

add nop

2026-06-02T18:58:26Z

commit 43306a63fb75f3320de54b7909f6d2003cd1872a parent 043c769061311f11e349da2aeeff74d7993d4656 Author: Vineet Kumar Date: Tue, 2 Jun 2026 14:58:26 -0400 add nop

replace writeback for loop with foreach

2026-06-02T18:58:18Z

commit 043c769061311f11e349da2aeeff74d7993d4656 parent 2bd38ff833475a49673216b0d9f9f12d0bb643d6 Author: Vineet Kumar Date: Tue, 2 Jun 2026 14:58:18 -0400 replace writeback for loop with foreach

move remaining decode typedefs to pkg for easier debugging access later

2026-06-02T02:57:58Z

commit 2bd38ff833475a49673216b0d9f9f12d0bb643d6 parent bc1680a2ed231c8b186acc46d958d8e0c0090833 Author: Vineet Kumar Date: Mon, 1 Jun 2026 22:57:58 -0400 move remaining decode typedefs to pkg for easier debugging access later

add stubs for unused signals in hart's top-level

2026-06-02T02:57:39Z

commit bc1680a2ed231c8b186acc46d958d8e0c0090833 parent 22609eac8bfa675d069b1967f8c6fef7f5ea1d28 Author: Vineet Kumar Date: Mon, 1 Jun 2026 22:57:39 -0400 add stubs for unused signals in hart's top-level

add writeback stage

2026-06-02T01:19:14Z

commit 22609eac8bfa675d069b1967f8c6fef7f5ea1d28 parent 515c289c366231ce253950a2774c15eebc7bc379 Author: Vineet Kumar Date: Mon, 1 Jun 2026 21:19:14 -0400 add writeback stage

add memory stage

2026-06-02T00:14:35Z

commit 515c289c366231ce253950a2774c15eebc7bc379 parent fb189d59d5c8b1f339870a151775b9889a46fcc8 Author: Vineet Kumar Date: Mon, 1 Jun 2026 20:14:35 -0400 add memory stage

add execute stage

2026-06-01T22:01:11Z

commit fb189d59d5c8b1f339870a151775b9889a46fcc8 parent d233e76dcd37b3d6773d865129119f9c0afbf921 Author: Vineet Kumar Date: Mon, 1 Jun 2026 18:01:11 -0400 add execute stage

group control signals together when decoding based on major opcode

2026-06-01T19:53:28Z

commit d233e76dcd37b3d6773d865129119f9c0afbf921 parent 0697dae7c278f7d3b076fb1617d6c155b63e31fc Author: Vineet Kumar Date: Mon, 1 Jun 2026 15:53:28 -0400 group control signals together when decoding based on major opcode

make a package for user-defined types

2026-06-01T19:40:14Z

commit 0697dae7c278f7d3b076fb1617d6c155b63e31fc parent 01e6e1ad0d0252ae4279a94cbf21deee8300965e Author: Vineet Kumar Date: Mon, 1 Jun 2026 15:40:14 -0400 make a package for user-defined types

add basic exception signals

2026-06-01T19:24:22Z

commit 01e6e1ad0d0252ae4279a94cbf21deee8300965e parent fe95a0356ebe488c2fa337db35a2b49f0535e40d Author: Vineet Kumar Date: Mon, 1 Jun 2026 15:24:22 -0400 add basic exception signals

l'anthorpic fishe

2026-06-01T14:59:04Z

commit fe95a0356ebe488c2fa337db35a2b49f0535e40d parent 61d17e4035ae8cc359c1f812c5318e85e25a911b Author: Vineet Kumar Date: Mon, 1 Jun 2026 10:59:04 -0400 l'anthorpic fishe

assign control signals for all non-SYSTEM RV32I instructions

2026-06-01T01:48:37Z

commit 61d17e4035ae8cc359c1f812c5318e85e25a911b parent 8211eeff31624249a8a6b65081b8f31f3fe0325e Author: Vineet Kumar Date: Sun, 31 May 2026 21:48:37 -0400 assign control signals for all non-SYSTEM RV32I instructions they need me to find where in privileged isa defines what exceptions I should raise and stuff

define control signals

2026-05-31T23:04:13Z

commit 8211eeff31624249a8a6b65081b8f31f3fe0325e parent b912995e94db9b6dad3d569897771ac3336e66ea Author: Vineet Kumar Date: Sun, 31 May 2026 19:04:13 -0400 define control signals

parse instructions into names to generate control signals

2026-05-31T21:26:14Z

commit b912995e94db9b6dad3d569897771ac3336e66ea parent dd7a05cc0e99dde0c7c9db643ffbe2bacf84d186 Author: Vineet Kumar Date: Sun, 31 May 2026 17:26:14 -0400 parse instructions into names to generate control signals

switch decoding to using major opcode enum

2026-05-31T20:48:01Z

commit dd7a05cc0e99dde0c7c9db643ffbe2bacf84d186 parent 81967b075efc78e269e45871a96782d240537724 Author: Vineet Kumar Date: Sun, 31 May 2026 16:48:01 -0400 switch decoding to using major opcode enum

start working on decoding logic

2026-05-31T19:58:30Z

commit 81967b075efc78e269e45871a96782d240537724 parent 7efe51f2eeacbb4b6b0d533e3384317b3fed7585 Author: Vineet Kumar Date: Sun, 31 May 2026 15:58:30 -0400 start working on decoding logic

fix regfile declaration to be an unpacked array

2026-05-30T19:21:45Z

commit 7efe51f2eeacbb4b6b0d533e3384317b3fed7585 parent 005a8afbb9eeaa3bda780697485b6b8b244102c3 Author: Vineet Kumar Date: Sat, 30 May 2026 15:21:45 -0400 fix regfile declaration to be an unpacked array

add fetching support but needs tests

2026-05-29T06:07:52Z

commit 005a8afbb9eeaa3bda780697485b6b8b244102c3 parent f3051150934a71265497e9b012df43c53349aca4 Author: Vineet Kumar Date: Fri, 29 May 2026 02:07:52 -0400 add fetching support but needs tests

add skeleton hart's top-level module with regfile

2026-05-29T03:01:02Z

commit f3051150934a71265497e9b012df43c53349aca4 parent fe8d12d6d81cb3e47b2308224cec6d855cdd6e5c Author: Vineet Kumar Date: Thu, 28 May 2026 23:01:02 -0400 add skeleton hart's top-level module with regfile

initial payload

2026-05-27T20:39:09Z

commit fe8d12d6d81cb3e47b2308224cec6d855cdd6e5c Author: Vineet Kumar Date: Wed, 27 May 2026 16:39:09 -0400 initial payload