From e1cdd7386807050bdd7db7debb902425a78e2970 Mon Sep 17 00:00:00 2001 From: vin Date: Thu, 4 Jul 2024 15:06:15 -0400 Subject: [PATCH] implement all of the nestest unofficial opcodes and fix branch cycles --- cpu.c | 19 ++++++++------- cpu.h | 2 +- opcodes.h | 70 +++++++++++++++++++++++++++---------------------------- 3 files changed, 46 insertions(+), 45 deletions(-) diff --git a/cpu.c b/cpu.c index 039337f..1345d8b 100644 --- a/cpu.c +++ b/cpu.c @@ -127,9 +127,7 @@ opcode_mem(enum addressing_mode mode) val = (arg + regs.y) % 256; break; case AM_REL: - val = arg + regs.pc; - if (((regs.pc + 1) & 0xFF00) != (val & 0xFF00)) - val -= 0x0100; + val = (int8_t)arg + regs.pc; break; case AM_IMM: case AM_ABS: @@ -174,6 +172,9 @@ branch(uint16_t addr, bool cond) return; cycles++; + if (((regs.pc + 1) & 0xFF00) != (addr & 0xFF00)) + cycles++; + regs.pc = addr; } @@ -277,7 +278,7 @@ BRK(uint16_t arg) { /* TODO: push regs.pc and regs.status to stack and load IRQ vector */ regs.status.brk = 1; - // exit(0); + exit(0); } void @@ -771,11 +772,11 @@ DCP(uint16_t arg) memwrite(arg, tmp); regs.status.carry = tmp <= regs.a; - STATUS_UPDATE_NZ(tmp); + STATUS_UPDATE_NZ(regs.a - tmp); } void -ISC(uint16_t arg) +ISB(uint16_t arg) { INC(arg); SBC(peek(arg)); @@ -807,7 +808,7 @@ void RLA(uint16_t arg) { ROL(arg); - AND(arg); + AND(peek(arg)); } void @@ -821,14 +822,14 @@ void SLO(uint16_t arg) { ASL(arg); - ORA(arg); + ORA(peek(arg)); } void SRE(uint16_t arg) { LSR(arg); - EOR(arg); + EOR(peek(arg)); } void diff --git a/cpu.h b/cpu.h index 3002573..ed17432 100644 --- a/cpu.h +++ b/cpu.h @@ -72,7 +72,7 @@ void AXA(uint16_t arg); void AXS(uint16_t arg); void DCP(uint16_t arg); void DOP(uint16_t arg); -void ISC(uint16_t arg); +void ISB(uint16_t arg); void KIL(uint16_t arg); void LAR(uint16_t arg); void LAX(uint16_t arg); diff --git a/opcodes.h b/opcodes.h index 020e8f3..89d5f73 100644 --- a/opcodes.h +++ b/opcodes.h @@ -220,13 +220,13 @@ struct opcode opcodes[0x100] = { [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, - [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, - [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, - [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, - [0xFF] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_X }, - [0xFB] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_Y }, - [0xE3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_X }, - [0xF3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_Y }, + [0xE7] = { "ISB", ISB, 2, 5, false, true, false, true, AM_ZP }, + [0xF7] = { "ISB", ISB, 2, 6, false, true, false, true, AM_ZP_X }, + [0xEF] = { "ISB", ISB, 3, 6, false, true, false, true, AM_ABS }, + [0xFF] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_X }, + [0xFB] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_Y }, + [0xE3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_X }, + [0xF3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_Y }, [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, @@ -252,35 +252,35 @@ struct opcode opcodes[0x100] = { [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, - [0x27] = { "RLA", RLA, 2, 5, true, true, false, true, AM_ZP }, - [0x37] = { "RLA", RLA, 2, 6, true, true, false, true, AM_ZP_X }, - [0x2F] = { "RLA", RLA, 3, 6, true, true, false, true, AM_ABS }, - [0x3F] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_X }, - [0x3B] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_Y }, - [0x23] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_X }, - [0x33] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_Y }, - [0x67] = { "RRA", RRA, 2, 5, true, true, false, true, AM_ZP }, - [0x77] = { "RRA", RRA, 2, 6, true, true, false, true, AM_ZP_X }, - [0x6F] = { "RRA", RRA, 3, 6, true, true, false, true, AM_ABS }, - [0x7F] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_X }, - [0x7B] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_Y }, - [0x63] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_X }, - [0x73] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_Y }, + [0x27] = { "RLA", RLA, 2, 5, false, true, false, true, AM_ZP }, + [0x37] = { "RLA", RLA, 2, 6, false, true, false, true, AM_ZP_X }, + [0x2F] = { "RLA", RLA, 3, 6, false, true, false, true, AM_ABS }, + [0x3F] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_X }, + [0x3B] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_Y }, + [0x23] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_X }, + [0x33] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_Y }, + [0x67] = { "RRA", RRA, 2, 5, false, true, false, true, AM_ZP }, + [0x77] = { "RRA", RRA, 2, 6, false, true, false, true, AM_ZP_X }, + [0x6F] = { "RRA", RRA, 3, 6, false, true, false, true, AM_ABS }, + [0x7F] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_X }, + [0x7B] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_Y }, + [0x63] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_X }, + [0x73] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_Y }, [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, - [0x07] = { "SLO", SLO, 2, 5, true, true, false, true, AM_ZP }, - [0x17] = { "SLO", SLO, 2, 6, true, true, false, true, AM_ZP_X }, - [0x0F] = { "SLO", SLO, 3, 6, true, true, false, true, AM_ABS }, - [0x1F] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_X }, - [0x1B] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_Y }, - [0x03] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_X }, - [0x13] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_Y }, - [0x47] = { "SRE", SRE, 2, 5, true, true, false, true, AM_ZP }, - [0x57] = { "SRE", SRE, 2, 6, true, true, false, true, AM_ZP_X }, - [0x4F] = { "SRE", SRE, 3, 6, true, true, false, true, AM_ABS }, - [0x5F] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_X }, - [0x5B] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_Y }, - [0x43] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_X }, - [0x53] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_Y }, + [0x07] = { "SLO", SLO, 2, 5, false, true, false, true, AM_ZP }, + [0x17] = { "SLO", SLO, 2, 6, false, true, false, true, AM_ZP_X }, + [0x0F] = { "SLO", SLO, 3, 6, false, true, false, true, AM_ABS }, + [0x1F] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_X }, + [0x1B] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_Y }, + [0x03] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_X }, + [0x13] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_Y }, + [0x47] = { "SRE", SRE, 2, 5, false, true, false, true, AM_ZP }, + [0x57] = { "SRE", SRE, 2, 6, false, true, false, true, AM_ZP_X }, + [0x4F] = { "SRE", SRE, 3, 6, false, true, false, true, AM_ABS }, + [0x5F] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_X }, + [0x5B] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_Y }, + [0x43] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_X }, + [0x53] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_Y }, [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y }, [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X }, [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS },