vin
1f6e3b054c
They're both the same and the compiler might have already optimized it away. It also conveys the message better in my opinion.
1453 lines
22 KiB
C
1453 lines
22 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define MAX(a, b) ((a > b) ? a : b)
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#define STATUS_UPDATE_ZERO(r) \
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(regs.status.zero = r == 0)
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#define STATUS_UPDATE_NEGATIVE(r) \
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(regs.status.negative = ((r & (1 << 7)) != 0))
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#define MEMORY_MIRROR(addr) \
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if (addr < 0x2000) \
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addr &= 0x07FF; \
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else if (addr < 0x4000) \
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addr &= 0x2007;
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#define PUSH(b) \
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(memwrite(0x0100 + regs.sp--, b))
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#define PULL() \
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(peek(0x0100 + regs.sp++))
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struct cpu_flags {
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uint8_t carry : 1;
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uint8_t zero : 1;
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uint8_t interrupt_disable : 1;
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uint8_t decimal_mode : 1;
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uint8_t brk : 1;
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uint8_t unused : 1;
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uint8_t overflow : 1;
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uint8_t negative : 1;
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};
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struct registers {
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uint8_t a, x, y, sp;
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struct cpu_flags status;
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uint16_t pc;
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};
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struct registers regs;
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enum addressing_mode {
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AM_IMM,
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AM_ZP,
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AM_ZP_X,
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AM_ZP_Y,
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AM_REL,
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AM_ABS,
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AM_ABS_X,
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AM_ABS_Y,
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AM_IND,
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AM_IND_X,
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AM_IND_Y,
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};
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/* 64K address space, 16bit words */
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uint8_t memory[0x16000];
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/* example program taken from https://bugzmanov.github.io/nes_ebook/chapter_3_1.html */
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uint8_t program[] = { 0xa9, 0xc0, 0xaa, 0xe8, 0x00 };
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uint32_t cycles = 0;
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static uint8_t
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peek(uint16_t addr)
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{
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MEMORY_MIRROR(addr);
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return memory[addr];
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}
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static uint16_t
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peek16(uint16_t addr)
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{
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MEMORY_MIRROR(addr);
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/* bytes are stored in little-endian (low then high) */
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return (uint16_t)memory[addr] | ((uint16_t)memory[addr + 1] << 8);
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}
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static void
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memwrite(uint16_t addr, uint8_t byte)
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{
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MEMORY_MIRROR(addr);
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memory[addr] = byte;
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}
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static void
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memwrite16(uint16_t addr, uint16_t word)
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{
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MEMORY_MIRROR(addr);
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/* bytes are stored in little-endian (low then high) */
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memory[addr] = word & 0xFF;
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memory[addr + 1] = (word & 0xFF00) >> 8;
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}
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static uint8_t
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opcode_arg(enum addressing_mode mode)
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{
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uint8_t arg, val;
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if (mode != AM_ABS && mode != AM_ABS_X && mode != AM_ABS_Y)
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arg = peek(regs.pc++);
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else
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arg = peek16(regs.pc), regs.pc += 2;
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switch (mode) {
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case AM_IMM:
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case AM_REL:
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val = arg;
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break;
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case AM_ZP:
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val = peek(arg % 256);
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break;
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case AM_ZP_X:
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val = peek((arg + regs.x) % 256);
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break;
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case AM_ZP_Y:
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val = peek((arg + regs.y) % 256);
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break;
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case AM_ABS:
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val = peek16(arg);
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break;
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case AM_ABS_X:
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val = peek16(arg + regs.x);
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break;
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case AM_ABS_Y:
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val = peek16(arg + regs.y);
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break;
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case AM_IND_X:
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val = peek(peek((arg + regs.x) % 256) + peek((arg + regs.x + 1) % 256) * 256);
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break;
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case AM_IND_Y:
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val = peek(peek(arg) + peek((arg + 1) % 256) * 256 + regs.y);
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break;
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default:
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fprintf(stderr, "INVALID ADDRESSING MODE\n");
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abort();
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}
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return val;
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}
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static uint16_t
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opcode_mem(enum addressing_mode mode)
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{
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uint8_t arg;
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uint16_t val;
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if (mode != AM_ABS && mode != AM_ABS_X && mode != AM_ABS_Y)
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arg = peek(regs.pc++);
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else
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arg = peek16(regs.pc), regs.pc += 2;
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switch (mode) {
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case AM_ZP:
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val = arg % 256;
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break;
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case AM_ZP_X:
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val = (arg + regs.x) % 256;
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break;
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case AM_ZP_Y:
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val = (arg + regs.y) % 256;
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break;
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case AM_ABS:
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val = arg;
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break;
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case AM_ABS_X:
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val = arg + regs.x;
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break;
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case AM_ABS_Y:
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val = arg + regs.y;
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break;
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case AM_IND_X:
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val = peek((arg + regs.x) % 256) + peek((arg + regs.x + 1) % 256) * 256;
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break;
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case AM_IND_Y:
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val = peek(arg) + peek((arg + 1) % 256) * 256 + regs.y;
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break;
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default:
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fprintf(stderr, "INVALID ADDRESSING MODE\n");
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abort();
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}
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return val;
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}
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static void
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adc(uint8_t arg)
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{
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uint16_t sum; // 16-bit sum makes it easier to determine carry flag
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sum = regs.a + arg + regs.status.carry;
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regs.a = sum & 0xFF;
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regs.status.carry = sum > 0xFF;
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/* overflow flag formula: https://stackoverflow.com/a/29224684 */
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regs.status.overflow = (~(regs.a ^ arg) & (regs.a ^ sum) & 0x80) != 0;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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and(uint8_t arg)
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{
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regs.a &= arg;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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asl_acc(void)
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{
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uint16_t tmp;
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tmp = regs.a << 1;
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regs.a = tmp & 0xFF;
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regs.status.carry = tmp > 0xFF;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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asl(uint16_t mem)
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{
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uint16_t tmp;
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tmp = peek(mem) << 1;
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memwrite(mem, tmp & 0xFF);
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regs.status.carry = tmp > 0xFF;
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STATUS_UPDATE_ZERO(tmp);
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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bcc(uint8_t arg)
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{
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if (regs.status.carry == 0)
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regs.pc += arg;
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}
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static void
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bcs(uint8_t arg)
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{
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if (regs.status.carry == 1)
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regs.pc += arg;
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}
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static void
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beq(uint8_t arg)
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{
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if (regs.status.zero == 1)
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regs.pc += arg;
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}
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static void
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bit(uint8_t arg)
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{
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regs.status.zero = (regs.a & arg) == 0;
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regs.status.overflow = (arg & (1 << 6)) != 0;
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STATUS_UPDATE_NEGATIVE(arg);
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}
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static void
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bmi(uint8_t arg)
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{
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if (regs.status.negative == 1)
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regs.pc += arg;
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}
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static void
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bne(uint8_t arg)
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{
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if (regs.status.zero == 0)
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regs.pc += arg;
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}
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static void
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bpl(uint8_t arg)
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{
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if (regs.status.negative == 0)
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regs.pc += arg;
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}
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static void
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brk(void)
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{
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/* TODO: push regs.pc and regs.status to stack and load IRQ vector */
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regs.status.brk = 1;
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exit(0);
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}
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static void
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bvc(uint8_t arg)
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{
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if (regs.status.overflow == 0)
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regs.pc += arg;
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}
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static void
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bvs(uint8_t arg)
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{
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if (regs.status.overflow == 1)
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regs.pc += arg;
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}
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static void
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clc(void)
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{
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regs.status.carry = 0;
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}
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static void
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cld(void)
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{
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regs.status.decimal_mode = 0;
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}
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static void
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cli(void)
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{
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regs.status.interrupt_disable = 0;
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}
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static void
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clv(void)
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{
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regs.status.overflow = 0;
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}
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static void
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cmp(uint8_t arg)
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{
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uint8_t tmp;
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tmp = regs.a - arg;
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regs.status.carry = regs.a >= arg;
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regs.status.zero = regs.a == arg;
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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cpx(uint8_t arg)
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{
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uint8_t tmp;
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tmp = regs.x - arg;
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regs.status.carry = regs.x >= arg;
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regs.status.zero = regs.x == arg;
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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cpy(uint8_t arg)
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{
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uint8_t tmp;
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tmp = regs.y - arg;
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regs.status.carry = regs.y >= arg;
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regs.status.zero = regs.y == arg;
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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dec(uint16_t mem)
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{
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memwrite(mem, peek(mem) - 1);
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STATUS_UPDATE_ZERO(peek(mem));
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STATUS_UPDATE_NEGATIVE(peek(mem));
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}
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static void
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dex(void)
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{
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regs.x--;
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STATUS_UPDATE_ZERO(regs.x);
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STATUS_UPDATE_NEGATIVE(regs.x);
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}
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static void
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dey(void)
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{
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regs.y--;
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STATUS_UPDATE_ZERO(regs.y);
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STATUS_UPDATE_NEGATIVE(regs.y);
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}
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static void
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eor(uint8_t arg)
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{
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regs.a ^= arg;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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inc(uint16_t mem)
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{
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memwrite(mem, peek(mem) + 1);
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STATUS_UPDATE_ZERO(peek(mem));
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STATUS_UPDATE_NEGATIVE(peek(mem));
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}
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static void
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inx(void)
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{
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regs.x++;
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STATUS_UPDATE_ZERO(regs.x);
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STATUS_UPDATE_NEGATIVE(regs.x);
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}
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static void
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iny(void)
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{
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regs.y++;
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STATUS_UPDATE_ZERO(regs.y);
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STATUS_UPDATE_NEGATIVE(regs.y);
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}
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static void
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jmp(uint16_t arg)
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{
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regs.pc = arg;
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}
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static void
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jsr(uint16_t arg)
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{
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uint16_t tmp = regs.pc + 2;
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/*
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* first push high-byte of return address then low-byte
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* https://www.masswerk.at/6502/6502_instruction_set.html
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*/
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PUSH((tmp & 0xFF00) >> 8);
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PUSH(tmp & 0xFF);
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regs.pc = arg;
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}
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static void
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lda(uint8_t arg)
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{
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regs.a = arg;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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ldx(uint8_t arg)
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{
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regs.x = arg;
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STATUS_UPDATE_ZERO(regs.x);
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STATUS_UPDATE_NEGATIVE(regs.x);
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}
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static void
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ldy(uint8_t arg)
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{
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regs.y = arg;
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STATUS_UPDATE_ZERO(regs.y);
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STATUS_UPDATE_NEGATIVE(regs.y);
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}
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static void
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lsr_acc(void)
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{
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regs.status.carry = regs.a & 1; // bit 0 in carry
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regs.a >>= 1;
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regs.a &= ~(1 << 7); // bit 7 cleared
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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lsr(uint16_t mem)
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{
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uint8_t tmp;
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tmp = peek(mem);
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regs.status.carry = tmp & 1; // bit 0 in carry
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tmp >>= 1;
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tmp &= ~(1 << 7); // bit 7 cleared
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memwrite(mem, tmp);
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STATUS_UPDATE_ZERO(tmp);
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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nop(void)
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{
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return;
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}
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static void
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ora(uint8_t arg)
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{
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regs.a |= arg;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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pha(void)
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{
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PUSH(regs.a);
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}
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static void
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php(void)
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{
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uint8_t status;
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status = (regs.status.carry << 7) | (regs.status.zero << 6)
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| (regs.status.interrupt_disable << 5) | (regs.status.decimal_mode << 4)
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| (regs.status.brk << 3) | (regs.status.unused << 2)
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| (regs.status.overflow << 1) | regs.status.negative;
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PUSH(status);
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}
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static void
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pla(void)
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{
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regs.a = PULL();
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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plp(void)
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{
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uint8_t status;
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status = PULL();
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regs.status.carry = (status & (1 << 7)) != 0;
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regs.status.zero = (status & (1 << 6)) != 0;
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regs.status.interrupt_disable = (status & (1 << 5)) != 0;
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regs.status.decimal_mode = (status & (1 << 4)) != 0;
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regs.status.brk = (status & (1 << 3)) != 0;
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regs.status.unused = (status & (1 << 2)) != 0;
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regs.status.overflow = (status & (1 << 1)) != 0;
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regs.status.negative = (status & 1) != 0;
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}
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static void
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rol_acc(void)
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{
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uint8_t carry;
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carry = (regs.a & (1 << 7)) != 0;
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regs.a <<= 1;
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regs.a |= regs.status.carry;
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regs.status.carry = carry;
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STATUS_UPDATE_ZERO(regs.a);
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STATUS_UPDATE_NEGATIVE(regs.a);
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}
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static void
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rol(uint16_t mem)
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{
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uint8_t carry, tmp;
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carry = (peek(mem) & (1 << 7)) != 0;
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tmp = (peek(mem) << 1) | regs.status.carry;
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memwrite(mem, tmp);
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regs.status.carry = carry;
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STATUS_UPDATE_ZERO(tmp);
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STATUS_UPDATE_NEGATIVE(tmp);
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}
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static void
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ror_acc(void)
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{
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uint8_t carry;
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carry = regs.a & 1;
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regs.a >>= 1;
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regs.a |= regs.status.carry << 7;
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regs.status.carry = carry;
|
|
STATUS_UPDATE_ZERO(regs.a);
|
|
STATUS_UPDATE_NEGATIVE(regs.a);
|
|
}
|
|
|
|
static void
|
|
ror(uint16_t mem)
|
|
{
|
|
uint8_t carry, tmp;
|
|
carry = peek(mem) & 1;
|
|
|
|
tmp = (peek(mem) >> 1) | (regs.status.carry << 7);
|
|
memwrite(mem, tmp);
|
|
|
|
regs.status.carry = carry;
|
|
STATUS_UPDATE_ZERO(tmp);
|
|
STATUS_UPDATE_NEGATIVE(tmp);
|
|
}
|
|
|
|
static void
|
|
rti(void)
|
|
{
|
|
plp();
|
|
regs.pc = PULL();
|
|
}
|
|
|
|
static void
|
|
rts(void)
|
|
{
|
|
regs.pc = PULL() + 1;
|
|
}
|
|
|
|
static void
|
|
sbc(uint8_t arg)
|
|
{
|
|
/* SBC is described online as ADC with argument as two's complement */
|
|
adc(~arg + 1);
|
|
}
|
|
|
|
static void
|
|
sec(void)
|
|
{
|
|
regs.status.carry = 1;
|
|
}
|
|
|
|
static void
|
|
sed(void)
|
|
{
|
|
regs.status.decimal_mode = 1;
|
|
}
|
|
|
|
static void
|
|
sei(void)
|
|
{
|
|
regs.status.interrupt_disable = 1;
|
|
}
|
|
|
|
static void
|
|
sta(uint16_t mem)
|
|
{
|
|
memwrite(mem, regs.a);
|
|
}
|
|
|
|
static void
|
|
stx(uint16_t mem)
|
|
{
|
|
memwrite(mem, regs.x);
|
|
}
|
|
|
|
static void
|
|
sty(uint16_t mem)
|
|
{
|
|
memwrite(mem, regs.y);
|
|
}
|
|
|
|
static void
|
|
tax(void)
|
|
{
|
|
regs.x = regs.a;
|
|
|
|
STATUS_UPDATE_ZERO(regs.x);
|
|
STATUS_UPDATE_NEGATIVE(regs.x);
|
|
}
|
|
|
|
static void
|
|
tay(void)
|
|
{
|
|
regs.y = regs.a;
|
|
|
|
STATUS_UPDATE_ZERO(regs.y);
|
|
STATUS_UPDATE_NEGATIVE(regs.y);
|
|
}
|
|
|
|
static void
|
|
tsx(void)
|
|
{
|
|
regs.x = PULL();
|
|
|
|
STATUS_UPDATE_ZERO(regs.x);
|
|
STATUS_UPDATE_NEGATIVE(regs.x);
|
|
}
|
|
|
|
static void
|
|
txa(void)
|
|
{
|
|
regs.a = regs.x;
|
|
|
|
STATUS_UPDATE_ZERO(regs.a);
|
|
STATUS_UPDATE_NEGATIVE(regs.a);
|
|
}
|
|
|
|
static void
|
|
txs(void)
|
|
{
|
|
PUSH(regs.x);
|
|
}
|
|
|
|
static void
|
|
tya(void)
|
|
{
|
|
regs.a = regs.y;
|
|
|
|
STATUS_UPDATE_ZERO(regs.a);
|
|
STATUS_UPDATE_NEGATIVE(regs.a);
|
|
}
|
|
|
|
static void
|
|
interpret(void)
|
|
{
|
|
uint8_t opcode;
|
|
|
|
for (;;) {
|
|
opcode = peek(regs.pc++);
|
|
|
|
printf("opcode: $%02X\n", opcode);
|
|
|
|
switch (opcode) {
|
|
case 0x69:
|
|
adc(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x65:
|
|
adc(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0x75:
|
|
adc(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x6d:
|
|
adc(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0x7d:
|
|
adc(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x79:
|
|
adc(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0x72:
|
|
adc(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0x61:
|
|
adc(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x71:
|
|
adc(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0x29:
|
|
and(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x25:
|
|
and(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0x35:
|
|
and(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x2d:
|
|
and(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0x3d:
|
|
and(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x39:
|
|
and(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0x32:
|
|
and(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0x21:
|
|
and(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x31:
|
|
and(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0x0a:
|
|
asl_acc();
|
|
cycles += 2;
|
|
break;
|
|
case 0x06:
|
|
asl(opcode_arg(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0x16:
|
|
asl(opcode_arg(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x0e:
|
|
asl(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0x1e:
|
|
asl(opcode_arg(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x90:
|
|
bcc(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xb0:
|
|
bcs(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xf0:
|
|
beq(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x89:
|
|
bit(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x24:
|
|
bit(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0x34:
|
|
bit(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x2c:
|
|
bit(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0x3c:
|
|
bit(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x30:
|
|
bmi(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xd0:
|
|
bne(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x10:
|
|
bpl(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x00:
|
|
brk();
|
|
cycles += 7;
|
|
break;
|
|
case 0x50:
|
|
bvc(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x70:
|
|
bvs(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x18:
|
|
clc();
|
|
cycles += 2;
|
|
break;
|
|
case 0xd8:
|
|
cld();
|
|
cycles += 2;
|
|
break;
|
|
case 0x58:
|
|
cli();
|
|
cycles += 2;
|
|
break;
|
|
case 0xb8:
|
|
clv();
|
|
cycles += 2;
|
|
break;
|
|
case 0xc9:
|
|
cmp(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xc5:
|
|
cmp(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xd5:
|
|
cmp(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xcd:
|
|
cmp(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xdd:
|
|
cmp(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xd9:
|
|
cmp(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0xd2:
|
|
cmp(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0xc1:
|
|
cmp(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xd1:
|
|
cmp(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0xe0:
|
|
cpx(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xe4:
|
|
cpx(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xec:
|
|
cpx(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xc0:
|
|
cpy(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xc4:
|
|
cpy(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xcc:
|
|
cpy(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xc6:
|
|
dec(opcode_mem(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0xd6:
|
|
dec(opcode_mem(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xce:
|
|
dec(opcode_mem(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0xde:
|
|
dec(opcode_mem(AM_ABS_X));
|
|
cycles += 7;
|
|
break;
|
|
case 0xca:
|
|
dex();
|
|
cycles += 2;
|
|
break;
|
|
case 0x88:
|
|
dey();
|
|
cycles += 2;
|
|
break;
|
|
case 0x49:
|
|
eor(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x45:
|
|
eor(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0x55:
|
|
eor(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x4d:
|
|
eor(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0x5d:
|
|
eor(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x59:
|
|
eor(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0x52:
|
|
eor(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0x41:
|
|
eor(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x51:
|
|
eor(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0xe6:
|
|
inc(opcode_arg(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0xf6:
|
|
inc(opcode_arg(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xee:
|
|
inc(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0xfe:
|
|
inc(opcode_arg(AM_ABS_X));
|
|
cycles += 7;
|
|
break;
|
|
case 0xe8:
|
|
inx();
|
|
cycles += 2;
|
|
break;
|
|
case 0xc8:
|
|
iny();
|
|
cycles += 2;
|
|
break;
|
|
case 0x4c:
|
|
jmp(opcode_arg(AM_ABS));
|
|
cycles += 3;
|
|
break;
|
|
case 0x6c:
|
|
jmp(opcode_arg(AM_IND));
|
|
cycles += 6;
|
|
break;
|
|
case 0x7c:
|
|
jmp(opcode_arg(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x20:
|
|
jsr(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0xa9:
|
|
lda(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xa5:
|
|
lda(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xb5:
|
|
lda(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xad:
|
|
lda(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xbd:
|
|
lda(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xb9:
|
|
lda(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0xb2:
|
|
lda(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0xa1:
|
|
lda(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xb1:
|
|
lda(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0xa2:
|
|
ldx(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xa6:
|
|
ldx(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xb6:
|
|
ldx(opcode_arg(AM_ZP_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0xae:
|
|
ldx(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xbe:
|
|
ldx(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0xa0:
|
|
ldy(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xa4:
|
|
ldy(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xb4:
|
|
ldy(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xac:
|
|
ldy(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xbc:
|
|
ldy(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x4a:
|
|
lsr_acc();
|
|
cycles += 2;
|
|
break;
|
|
case 0x46:
|
|
lsr(opcode_arg(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0x56:
|
|
lsr(opcode_arg(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x4e:
|
|
lsr(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0x5e:
|
|
lsr(opcode_arg(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xea:
|
|
nop();
|
|
cycles += 2;
|
|
break;
|
|
case 0x09:
|
|
ora(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0x05:
|
|
ora(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0x15:
|
|
ora(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x0d:
|
|
ora(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0x1d:
|
|
ora(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0x19:
|
|
ora(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0x12:
|
|
ora(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0x01:
|
|
ora(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x11:
|
|
ora(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0x48:
|
|
pha();
|
|
cycles += 3;
|
|
break;
|
|
case 0x08:
|
|
php();
|
|
cycles += 3;
|
|
break;
|
|
case 0x68:
|
|
pla();
|
|
cycles += 4;
|
|
break;
|
|
case 0x28:
|
|
plp();
|
|
cycles += 4;
|
|
break;
|
|
case 0x2a:
|
|
rol_acc();
|
|
cycles += 2;
|
|
break;
|
|
case 0x26:
|
|
rol(opcode_arg(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0x36:
|
|
rol(opcode_arg(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x2e:
|
|
rol(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0x3e:
|
|
rol(opcode_arg(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x6a:
|
|
ror_acc();
|
|
cycles += 2;
|
|
break;
|
|
case 0x66:
|
|
ror(opcode_arg(AM_ZP));
|
|
cycles += 5;
|
|
break;
|
|
case 0x76:
|
|
ror(opcode_arg(AM_ZP_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x6e:
|
|
ror(opcode_arg(AM_ABS));
|
|
cycles += 6;
|
|
break;
|
|
case 0x7e:
|
|
ror(opcode_arg(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x40:
|
|
rti();
|
|
cycles += 6;
|
|
break;
|
|
case 0x60:
|
|
rts();
|
|
cycles += 6;
|
|
break;
|
|
case 0xe9:
|
|
sbc(opcode_arg(AM_IMM));
|
|
cycles += 2;
|
|
break;
|
|
case 0xe5:
|
|
sbc(opcode_arg(AM_ZP));
|
|
cycles += 3;
|
|
break;
|
|
case 0xf5:
|
|
sbc(opcode_arg(AM_ZP_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xed:
|
|
sbc(opcode_arg(AM_ABS));
|
|
cycles += 4;
|
|
break;
|
|
case 0xfd:
|
|
sbc(opcode_arg(AM_ABS_X));
|
|
cycles += 4;
|
|
break;
|
|
case 0xf9:
|
|
sbc(opcode_arg(AM_ABS_Y));
|
|
cycles += 4;
|
|
break;
|
|
case 0xf2:
|
|
sbc(opcode_arg(AM_IND));
|
|
cycles += 5;
|
|
break;
|
|
case 0xe1:
|
|
sbc(opcode_arg(AM_IND_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0xf1:
|
|
sbc(opcode_arg(AM_IND_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0x38:
|
|
sec();
|
|
cycles += 2;
|
|
break;
|
|
case 0xf8:
|
|
sed();
|
|
cycles += 2;
|
|
break;
|
|
case 0x78:
|
|
sei();
|
|
cycles += 2;
|
|
break;
|
|
case 0x85:
|
|
sta(opcode_mem(AM_ZP));
|
|
cycles += 4;
|
|
break;
|
|
case 0x95:
|
|
sta(opcode_mem(AM_ZP_X));
|
|
cycles += 5;
|
|
break;
|
|
case 0x8d:
|
|
sta(opcode_mem(AM_ABS));
|
|
cycles += 5;
|
|
break;
|
|
case 0x9d:
|
|
sta(opcode_mem(AM_ABS_X));
|
|
cycles += 6;
|
|
break;
|
|
case 0x99:
|
|
sta(opcode_mem(AM_ABS_Y));
|
|
cycles += 6;
|
|
break;
|
|
case 0x92:
|
|
sta(opcode_mem(AM_IND));
|
|
cycles += 6;
|
|
break;
|
|
case 0x81:
|
|
sta(opcode_mem(AM_IND_X));
|
|
cycles += 7;
|
|
break;
|
|
case 0x91:
|
|
sta(opcode_mem(AM_IND_Y));
|
|
cycles += 7;
|
|
break;
|
|
case 0x86:
|
|
stx(opcode_mem(AM_ZP));
|
|
cycles += 4;
|
|
break;
|
|
case 0x96:
|
|
stx(opcode_mem(AM_ZP_Y));
|
|
cycles += 5;
|
|
break;
|
|
case 0x8e:
|
|
stx(opcode_mem(AM_ABS));
|
|
cycles += 5;
|
|
break;
|
|
case 0x84:
|
|
sty(opcode_mem(AM_ZP));
|
|
cycles += 4;
|
|
break;
|
|
case 0x94:
|
|
sty(opcode_mem(AM_ZP_X));
|
|
cycles += 5;
|
|
break;
|
|
case 0x8c:
|
|
sty(opcode_mem(AM_ABS));
|
|
cycles += 5;
|
|
break;
|
|
case 0xaa:
|
|
tax();
|
|
cycles += 2;
|
|
break;
|
|
case 0xa8:
|
|
tay();
|
|
cycles += 2;
|
|
break;
|
|
case 0xba:
|
|
tsx();
|
|
cycles += 2;
|
|
break;
|
|
case 0x8a:
|
|
txa();
|
|
cycles += 2;
|
|
break;
|
|
case 0x9a:
|
|
txs();
|
|
cycles += 2;
|
|
break;
|
|
case 0x98:
|
|
tya();
|
|
cycles += 2;
|
|
break;
|
|
default:
|
|
printf("opcode $%02X not implemented\n", opcode);
|
|
break;
|
|
}
|
|
|
|
printf("status: %i%i%i%i%i%i%i%i\n", regs.status.carry,
|
|
regs.status.zero, regs.status.interrupt_disable,
|
|
regs.status.decimal_mode, regs.status.brk,
|
|
regs.status.unused, regs.status.overflow,
|
|
regs.status.negative);
|
|
printf("A: $%02X, X: $%02X, Y: $%02X, SP: $%02X, PC: $%02X\n",
|
|
regs.a, regs.x, regs.y, regs.sp, regs.pc);
|
|
}
|
|
}
|
|
|
|
/* https://www.nesdev.org/wiki/CPU_power_up_state */
|
|
void
|
|
cpu_init(void)
|
|
{
|
|
regs.a = regs.x = regs.y = 0;
|
|
regs.pc = 0xFFFC;
|
|
regs.sp = 0xFD;
|
|
|
|
memset(®s.status, 0, sizeof(regs.status));
|
|
regs.status.unused = 1;
|
|
|
|
cycles += 7;
|
|
}
|
|
|
|
int
|
|
main(void)
|
|
{
|
|
cpu_init();
|
|
|
|
if (sizeof(program) > (0x10000 - 0x8000)) {
|
|
fprintf(stderr, "program is too big for memory\n");
|
|
return 1;
|
|
}
|
|
|
|
memcpy(memory + 0x8000, program, sizeof(program));
|
|
regs.pc = 0x8000;
|
|
|
|
printf("Initial State:\n");
|
|
printf("status: %i%i%i%i%i%i%i%i\n", regs.status.carry,
|
|
regs.status.zero, regs.status.interrupt_disable,
|
|
regs.status.decimal_mode, regs.status.brk,
|
|
regs.status.unused, regs.status.overflow,
|
|
regs.status.negative);
|
|
printf("A: $%02X, X: $%02X, Y: $%02X, SP: $%02X, PC: $%02X\n",
|
|
regs.a, regs.x, regs.y, regs.sp, regs.pc);
|
|
|
|
putchar('\n');
|
|
|
|
interpret();
|
|
|
|
return 0;
|
|
}
|