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remove unused libraries

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This commit is contained in:
Vineet K 2023-10-09 10:43:46 -04:00
parent 52db763c71
commit 797953ea2c
268 changed files with 0 additions and 26968 deletions
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18
.gitmodules vendored
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@ -1,14 +1,3 @@
[submodule "lib/chibios"]
path = lib/chibios
url = https://github.com/qmk/ChibiOS
branch = master
[submodule "lib/chibios-contrib"]
path = lib/chibios-contrib
url = https://github.com/qmk/ChibiOS-Contrib
branch = master
[submodule "lib/googletest"]
path = lib/googletest
url = https://github.com/qmk/googletest
[submodule "lib/lufa"] [submodule "lib/lufa"]
path = lib/lufa path = lib/lufa
url = https://github.com/qmk/lufa url = https://github.com/qmk/lufa
@ -18,10 +7,3 @@
[submodule "lib/printf"] [submodule "lib/printf"]
path = lib/printf path = lib/printf
url = https://github.com/qmk/printf url = https://github.com/qmk/printf
[submodule "lib/pico-sdk"]
path = lib/pico-sdk
url = https://github.com/qmk/pico-sdk.git
[submodule "lib/lvgl"]
path = lib/lvgl
url = https://github.com/qmk/lvgl.git
branch = release/v8.2

1
lib/chibios

@ -1 +0,0 @@
Subproject commit 11edb1610980f213b9f83161e1715a46fb7e4c51

1
lib/chibios-contrib

@ -1 +0,0 @@
Subproject commit da78eb3759b8d1779b237657c7667baa4aa95ca1

1
lib/googletest

@ -1 +0,0 @@
Subproject commit e2239ee6043f73722e7aa812a459f54a28552929

1
lib/lvgl

@ -1 +0,0 @@
Subproject commit e19410f8f8a256609da72cff549598e0df6fa4cf

1
lib/pico-sdk

@ -1 +0,0 @@
Subproject commit a3398d8d3a772f37fef44a74743a1de69770e9c2

294
platforms/chibios/_pin_defs.h
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@ -1,294 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#if defined(MCU_KINETIS)
// TODO: including this avoids "error: expected identifier before '(' token" errors
// here just to please KINETIS builds...
# include <hal.h>
#endif
/* Include the vendor specific pin defs */
#if __has_include_next("_pin_defs.h")
# include_next "_pin_defs.h"
#endif
#define A0 PAL_LINE(GPIOA, 0)
#define A1 PAL_LINE(GPIOA, 1)
#define A2 PAL_LINE(GPIOA, 2)
#define A3 PAL_LINE(GPIOA, 3)
#define A4 PAL_LINE(GPIOA, 4)
#define A5 PAL_LINE(GPIOA, 5)
#define A6 PAL_LINE(GPIOA, 6)
#define A7 PAL_LINE(GPIOA, 7)
#define A8 PAL_LINE(GPIOA, 8)
#define A9 PAL_LINE(GPIOA, 9)
#define A10 PAL_LINE(GPIOA, 10)
#define A11 PAL_LINE(GPIOA, 11)
#define A12 PAL_LINE(GPIOA, 12)
#define A13 PAL_LINE(GPIOA, 13)
#define A14 PAL_LINE(GPIOA, 14)
#define A15 PAL_LINE(GPIOA, 15)
#define A16 PAL_LINE(GPIOA, 16)
#define A17 PAL_LINE(GPIOA, 17)
#define A18 PAL_LINE(GPIOA, 18)
#define A19 PAL_LINE(GPIOA, 19)
#define A20 PAL_LINE(GPIOA, 20)
#define A21 PAL_LINE(GPIOA, 21)
#define A22 PAL_LINE(GPIOA, 22)
#define A23 PAL_LINE(GPIOA, 23)
#define A24 PAL_LINE(GPIOA, 24)
#define A25 PAL_LINE(GPIOA, 25)
#define A26 PAL_LINE(GPIOA, 26)
#define A27 PAL_LINE(GPIOA, 27)
#define A28 PAL_LINE(GPIOA, 28)
#define A29 PAL_LINE(GPIOA, 29)
#define A30 PAL_LINE(GPIOA, 30)
#define A31 PAL_LINE(GPIOA, 31)
#define A32 PAL_LINE(GPIOA, 32)
#define B0 PAL_LINE(GPIOB, 0)
#define B1 PAL_LINE(GPIOB, 1)
#define B2 PAL_LINE(GPIOB, 2)
#define B3 PAL_LINE(GPIOB, 3)
#define B4 PAL_LINE(GPIOB, 4)
#define B5 PAL_LINE(GPIOB, 5)
#define B6 PAL_LINE(GPIOB, 6)
#define B7 PAL_LINE(GPIOB, 7)
#define B8 PAL_LINE(GPIOB, 8)
#define B9 PAL_LINE(GPIOB, 9)
#define B10 PAL_LINE(GPIOB, 10)
#define B11 PAL_LINE(GPIOB, 11)
#define B12 PAL_LINE(GPIOB, 12)
#define B13 PAL_LINE(GPIOB, 13)
#define B14 PAL_LINE(GPIOB, 14)
#define B15 PAL_LINE(GPIOB, 15)
#define B16 PAL_LINE(GPIOB, 16)
#define B17 PAL_LINE(GPIOB, 17)
#define B18 PAL_LINE(GPIOB, 18)
#define B19 PAL_LINE(GPIOB, 19)
#define B20 PAL_LINE(GPIOB, 20)
#define B21 PAL_LINE(GPIOB, 21)
#define B22 PAL_LINE(GPIOB, 22)
#define B23 PAL_LINE(GPIOB, 23)
#define B24 PAL_LINE(GPIOB, 24)
#define B25 PAL_LINE(GPIOB, 25)
#define B26 PAL_LINE(GPIOB, 26)
#define B27 PAL_LINE(GPIOB, 27)
#define B28 PAL_LINE(GPIOB, 28)
#define B29 PAL_LINE(GPIOB, 29)
#define B30 PAL_LINE(GPIOB, 30)
#define B31 PAL_LINE(GPIOB, 31)
#define B32 PAL_LINE(GPIOB, 32)
#define C0 PAL_LINE(GPIOC, 0)
#define C1 PAL_LINE(GPIOC, 1)
#define C2 PAL_LINE(GPIOC, 2)
#define C3 PAL_LINE(GPIOC, 3)
#define C4 PAL_LINE(GPIOC, 4)
#define C5 PAL_LINE(GPIOC, 5)
#define C6 PAL_LINE(GPIOC, 6)
#define C7 PAL_LINE(GPIOC, 7)
#define C8 PAL_LINE(GPIOC, 8)
#define C9 PAL_LINE(GPIOC, 9)
#define C10 PAL_LINE(GPIOC, 10)
#define C11 PAL_LINE(GPIOC, 11)
#define C12 PAL_LINE(GPIOC, 12)
#define C13 PAL_LINE(GPIOC, 13)
#define C14 PAL_LINE(GPIOC, 14)
#define C15 PAL_LINE(GPIOC, 15)
#define C16 PAL_LINE(GPIOC, 16)
#define C17 PAL_LINE(GPIOC, 17)
#define C18 PAL_LINE(GPIOC, 18)
#define C19 PAL_LINE(GPIOC, 19)
#define C20 PAL_LINE(GPIOC, 20)
#define C21 PAL_LINE(GPIOC, 21)
#define C22 PAL_LINE(GPIOC, 22)
#define C23 PAL_LINE(GPIOC, 23)
#define C24 PAL_LINE(GPIOC, 24)
#define C25 PAL_LINE(GPIOC, 25)
#define C26 PAL_LINE(GPIOC, 26)
#define C27 PAL_LINE(GPIOC, 27)
#define C28 PAL_LINE(GPIOC, 28)
#define C29 PAL_LINE(GPIOC, 29)
#define C30 PAL_LINE(GPIOC, 30)
#define C31 PAL_LINE(GPIOC, 31)
#define C32 PAL_LINE(GPIOC, 32)
#define D0 PAL_LINE(GPIOD, 0)
#define D1 PAL_LINE(GPIOD, 1)
#define D2 PAL_LINE(GPIOD, 2)
#define D3 PAL_LINE(GPIOD, 3)
#define D4 PAL_LINE(GPIOD, 4)
#define D5 PAL_LINE(GPIOD, 5)
#define D6 PAL_LINE(GPIOD, 6)
#define D7 PAL_LINE(GPIOD, 7)
#define D8 PAL_LINE(GPIOD, 8)
#define D9 PAL_LINE(GPIOD, 9)
#define D10 PAL_LINE(GPIOD, 10)
#define D11 PAL_LINE(GPIOD, 11)
#define D12 PAL_LINE(GPIOD, 12)
#define D13 PAL_LINE(GPIOD, 13)
#define D14 PAL_LINE(GPIOD, 14)
#define D15 PAL_LINE(GPIOD, 15)
#define D16 PAL_LINE(GPIOD, 16)
#define D17 PAL_LINE(GPIOD, 17)
#define D18 PAL_LINE(GPIOD, 18)
#define D19 PAL_LINE(GPIOD, 19)
#define D20 PAL_LINE(GPIOD, 20)
#define D21 PAL_LINE(GPIOD, 21)
#define D22 PAL_LINE(GPIOD, 22)
#define D23 PAL_LINE(GPIOD, 23)
#define D24 PAL_LINE(GPIOD, 24)
#define D25 PAL_LINE(GPIOD, 25)
#define D26 PAL_LINE(GPIOD, 26)
#define D27 PAL_LINE(GPIOD, 27)
#define D28 PAL_LINE(GPIOD, 28)
#define D29 PAL_LINE(GPIOD, 29)
#define D30 PAL_LINE(GPIOD, 30)
#define D31 PAL_LINE(GPIOD, 31)
#define D32 PAL_LINE(GPIOD, 32)
#define E0 PAL_LINE(GPIOE, 0)
#define E1 PAL_LINE(GPIOE, 1)
#define E2 PAL_LINE(GPIOE, 2)
#define E3 PAL_LINE(GPIOE, 3)
#define E4 PAL_LINE(GPIOE, 4)
#define E5 PAL_LINE(GPIOE, 5)
#define E6 PAL_LINE(GPIOE, 6)
#define E7 PAL_LINE(GPIOE, 7)
#define E8 PAL_LINE(GPIOE, 8)
#define E9 PAL_LINE(GPIOE, 9)
#define E10 PAL_LINE(GPIOE, 10)
#define E11 PAL_LINE(GPIOE, 11)
#define E12 PAL_LINE(GPIOE, 12)
#define E13 PAL_LINE(GPIOE, 13)
#define E14 PAL_LINE(GPIOE, 14)
#define E15 PAL_LINE(GPIOE, 15)
#define E16 PAL_LINE(GPIOE, 16)
#define E17 PAL_LINE(GPIOE, 17)
#define E18 PAL_LINE(GPIOE, 18)
#define E19 PAL_LINE(GPIOE, 19)
#define E20 PAL_LINE(GPIOE, 20)
#define E21 PAL_LINE(GPIOE, 21)
#define E22 PAL_LINE(GPIOE, 22)
#define E23 PAL_LINE(GPIOE, 23)
#define E24 PAL_LINE(GPIOE, 24)
#define E25 PAL_LINE(GPIOE, 25)
#define E26 PAL_LINE(GPIOE, 26)
#define E27 PAL_LINE(GPIOE, 27)
#define E28 PAL_LINE(GPIOE, 28)
#define E29 PAL_LINE(GPIOE, 29)
#define E30 PAL_LINE(GPIOE, 30)
#define E31 PAL_LINE(GPIOE, 31)
#define E32 PAL_LINE(GPIOE, 32)
#define F0 PAL_LINE(GPIOF, 0)
#define F1 PAL_LINE(GPIOF, 1)
#define F2 PAL_LINE(GPIOF, 2)
#define F3 PAL_LINE(GPIOF, 3)
#define F4 PAL_LINE(GPIOF, 4)
#define F5 PAL_LINE(GPIOF, 5)
#define F6 PAL_LINE(GPIOF, 6)
#define F7 PAL_LINE(GPIOF, 7)
#define F8 PAL_LINE(GPIOF, 8)
#define F9 PAL_LINE(GPIOF, 9)
#define F10 PAL_LINE(GPIOF, 10)
#define F11 PAL_LINE(GPIOF, 11)
#define F12 PAL_LINE(GPIOF, 12)
#define F13 PAL_LINE(GPIOF, 13)
#define F14 PAL_LINE(GPIOF, 14)
#define F15 PAL_LINE(GPIOF, 15)
#define G0 PAL_LINE(GPIOG, 0)
#define G1 PAL_LINE(GPIOG, 1)
#define G2 PAL_LINE(GPIOG, 2)
#define G3 PAL_LINE(GPIOG, 3)
#define G4 PAL_LINE(GPIOG, 4)
#define G5 PAL_LINE(GPIOG, 5)
#define G6 PAL_LINE(GPIOG, 6)
#define G7 PAL_LINE(GPIOG, 7)
#define G8 PAL_LINE(GPIOG, 8)
#define G9 PAL_LINE(GPIOG, 9)
#define G10 PAL_LINE(GPIOG, 10)
#define G11 PAL_LINE(GPIOG, 11)
#define G12 PAL_LINE(GPIOG, 12)
#define G13 PAL_LINE(GPIOG, 13)
#define G14 PAL_LINE(GPIOG, 14)
#define G15 PAL_LINE(GPIOG, 15)
#define H0 PAL_LINE(GPIOH, 0)
#define H1 PAL_LINE(GPIOH, 1)
#define H2 PAL_LINE(GPIOH, 2)
#define H3 PAL_LINE(GPIOH, 3)
#define H4 PAL_LINE(GPIOH, 4)
#define H5 PAL_LINE(GPIOH, 5)
#define H6 PAL_LINE(GPIOH, 6)
#define H7 PAL_LINE(GPIOH, 7)
#define H8 PAL_LINE(GPIOH, 8)
#define H9 PAL_LINE(GPIOH, 9)
#define H10 PAL_LINE(GPIOH, 10)
#define H11 PAL_LINE(GPIOH, 11)
#define H12 PAL_LINE(GPIOH, 12)
#define H13 PAL_LINE(GPIOH, 13)
#define H14 PAL_LINE(GPIOH, 14)
#define H15 PAL_LINE(GPIOH, 15)
#define I0 PAL_LINE(GPIOI, 0)
#define I1 PAL_LINE(GPIOI, 1)
#define I2 PAL_LINE(GPIOI, 2)
#define I3 PAL_LINE(GPIOI, 3)
#define I4 PAL_LINE(GPIOI, 4)
#define I5 PAL_LINE(GPIOI, 5)
#define I6 PAL_LINE(GPIOI, 6)
#define I7 PAL_LINE(GPIOI, 7)
#define I8 PAL_LINE(GPIOI, 8)
#define I9 PAL_LINE(GPIOI, 9)
#define I10 PAL_LINE(GPIOI, 10)
#define I11 PAL_LINE(GPIOI, 11)
#define I12 PAL_LINE(GPIOI, 12)
#define I13 PAL_LINE(GPIOI, 13)
#define I14 PAL_LINE(GPIOI, 14)
#define I15 PAL_LINE(GPIOI, 15)
#define J0 PAL_LINE(GPIOJ, 0)
#define J1 PAL_LINE(GPIOJ, 1)
#define J2 PAL_LINE(GPIOJ, 2)
#define J3 PAL_LINE(GPIOJ, 3)
#define J4 PAL_LINE(GPIOJ, 4)
#define J5 PAL_LINE(GPIOJ, 5)
#define J6 PAL_LINE(GPIOJ, 6)
#define J7 PAL_LINE(GPIOJ, 7)
#define J8 PAL_LINE(GPIOJ, 8)
#define J9 PAL_LINE(GPIOJ, 9)
#define J10 PAL_LINE(GPIOJ, 10)
#define J11 PAL_LINE(GPIOJ, 11)
#define J12 PAL_LINE(GPIOJ, 12)
#define J13 PAL_LINE(GPIOJ, 13)
#define J14 PAL_LINE(GPIOJ, 14)
#define J15 PAL_LINE(GPIOJ, 15)
// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole
// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the
// keyboard designer should use a different symbol when defining their layout macros.
#ifdef KEYBOARD_REQUIRES_GPIOK
# define K0 PAL_LINE(GPIOK, 0)
# define K1 PAL_LINE(GPIOK, 1)
# define K2 PAL_LINE(GPIOK, 2)
# define K3 PAL_LINE(GPIOK, 3)
# define K4 PAL_LINE(GPIOK, 4)
# define K5 PAL_LINE(GPIOK, 5)
# define K6 PAL_LINE(GPIOK, 6)
# define K7 PAL_LINE(GPIOK, 7)
# define K8 PAL_LINE(GPIOK, 8)
# define K9 PAL_LINE(GPIOK, 9)
# define K10 PAL_LINE(GPIOK, 10)
# define K11 PAL_LINE(GPIOK, 11)
# define K12 PAL_LINE(GPIOK, 12)
# define K13 PAL_LINE(GPIOK, 13)
# define K14 PAL_LINE(GPIOK, 14)
# define K15 PAL_LINE(GPIOK, 15)
#endif

19
platforms/chibios/_timer.h
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@ -1,19 +0,0 @@
/* Copyright 2021 Simon Arlott
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// The platform is 32-bit, so prefer 32-bit timers to avoid overflow
#define FAST_TIMER_T_SIZE 32

89
platforms/chibios/_wait.c
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@ -1,89 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OPTIMIZE__
# pragma message "Compiler optimizations disabled; wait_cpuclock() won't work as designed"
#endif
#define CLOCK_DELAY_NOP8 "nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t"
__attribute__((always_inline)) static inline void wait_cpuclock(unsigned int n) { /* n: 1..135 */
/* The argument n must be a constant expression.
* That way, compiler optimization will remove unnecessary code. */
if (n < 1) {
return;
}
if (n > 8) {
unsigned int n8 = n / 8;
n = n - n8 * 8;
switch (n8) {
case 16:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 15:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 14:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 13:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 12:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 11:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 10:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 9:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 8:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 7:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 6:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 5:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 4:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 3:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 2:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 1:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 0:
break;
}
}
switch (n) {
case 8:
asm volatile("nop" ::: "memory");
case 7:
asm volatile("nop" ::: "memory");
case 6:
asm volatile("nop" ::: "memory");
case 5:
asm volatile("nop" ::: "memory");
case 4:
asm volatile("nop" ::: "memory");
case 3:
asm volatile("nop" ::: "memory");
case 2:
asm volatile("nop" ::: "memory");
case 1:
asm volatile("nop" ::: "memory");
case 0:
break;
}
}

66
platforms/chibios/_wait.h
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@ -1,66 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <ch.h>
#include <hal.h>
#include "chibios_config.h"
/* chThdSleepX of zero maps to infinite - so we map to a tiny delay to still yield */
#define wait_ms(ms) \
do { \
if (ms != 0) { \
chThdSleepMilliseconds(ms); \
} else { \
chThdSleepMicroseconds(1); \
} \
} while (0)
#ifdef WAIT_US_TIMER
void wait_us(uint16_t duration);
#elif PORT_SUPPORTS_RT == TRUE
# define wait_us(us) \
do { \
chSysPolledDelayX(US2RTC(REALTIME_COUNTER_CLOCK, us)); \
} while (0)
#else
# define wait_us(us) \
do { \
if (us != 0) { \
chThdSleepMicroseconds(us); \
} else { \
chThdSleepMicroseconds(1); \
} \
} while (0)
#endif
#include "_wait.c"
/* For GPIOs on ARM-based MCUs, the input pins are sampled by the clock of the bus
* to which the GPIO is connected.
* The connected buses differ depending on the various series of MCUs.
* And since the instruction execution clock of the CPU and the bus clock of GPIO are different,
* there is a delay of several clocks to read the change of the input signal.
*
* Define this delay with the GPIO_INPUT_PIN_DELAY macro.
* If the GPIO_INPUT_PIN_DELAY macro is not defined, the following default values will be used.
* (A fairly large value of 0.25 microseconds is set.)
*/
#ifndef GPIO_INPUT_PIN_DELAY
# define GPIO_INPUT_PIN_DELAY (CPU_CLOCK / 1000000L / 4)
#endif
#define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)

48
platforms/chibios/atomic_util.h
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@ -1,48 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <ch.h>
static __inline__ uint8_t __interrupt_disable__(void) {
chSysLock();
return 1;
}
static __inline__ void __interrupt_enable__(const uint8_t *__s) {
chSysUnlock();
__asm__ volatile("" ::: "memory");
(void)__s;
}
static __inline__ syssts_t __interrupt_lock__(void) {
return chSysGetStatusAndLockX();
}
static __inline__ void __interrupt_unlock__(const syssts_t *__s) {
chSysRestoreStatusX(*__s);
__asm__ volatile("" ::: "memory");
}
#define ATOMIC_BLOCK(type) for (type, __ToDo = 1; __ToDo; __ToDo = 0)
#define ATOMIC_FORCEON uint8_t status_save __attribute__((__cleanup__(__interrupt_enable__))) = __interrupt_disable__()
#define ATOMIC_RESTORESTATE syssts_t status_save __attribute__((__cleanup__(__interrupt_unlock__))) = __interrupt_lock__()
#define ATOMIC_BLOCK_RESTORESTATE ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)

9
platforms/chibios/boards/BLACKPILL_STM32_F401/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

77
platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h
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@ -1,77 +0,0 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
// Force B9 as input to align with qmk defaults
#undef VAL_GPIOB_MODER
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_INPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_ALTERNATE(GPIOB_SWO) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_INPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#undef VAL_GPIOB_PUPDR
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_SWO) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#undef VAL_GPIOB_AFRL
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_SWO, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#undef VAL_GPIOB_AFRH
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#undef STM32_HSE_BYPASS

40
platforms/chibios/boards/BLACKPILL_STM32_F401/configs/config.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef STM32_LSECLK
# define STM32_LSECLK 32768U
#endif // STM32_LSECLK
#ifndef STM32_HSECLK
# define STM32_HSECLK 25000000U
#endif // STM32_HSECLK
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

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platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F401_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/BLACKPILL_STM32_F411/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/BLACKPILL_STM32_F411/configs/board.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSE_BYPASS

40
platforms/chibios/boards/BLACKPILL_STM32_F411/configs/config.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef STM32_LSECLK
# define STM32_LSECLK 32768U
#endif // STM32_LSECLK
#ifndef STM32_HSECLK
# define STM32_HSECLK 25000000U
#endif // STM32_HSECLK
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

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platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F411_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 8
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/BONSAI_C4/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/BONSAI_C4/configs/board.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSE_BYPASS

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platforms/chibios/boards/BONSAI_C4/configs/config.h
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/* Copyright 2022 David Hoelscher, customMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
// Bonsai C4 includes Vbus sensing; derived designs that use PA9 for other purposes
// may disable Vbus sensing with #define BOARD_OTG_NOVBUSSENS 1
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
// FRAM configuration
#ifndef EXTERNAL_EEPROM_SPI_SLAVE_SELECT_PIN
# define EXTERNAL_EEPROM_SPI_SLAVE_SELECT_PIN PAL_LINE(GPIOA, 0)
# define EXTERNAL_EEPROM_SPI_CLOCK_DIVISOR 8 // 96MHz / 8 = 12MHz; max supported by MB85R64 is 20MHz
# define EXTERNAL_EEPROM_BYTE_COUNT 8192
# define EXTERNAL_EEPROM_PAGE_SIZE 64 // does not matter for FRAM, just sets the RAM buffer size in STM32F chip
# define DYNAMIC_KEYMAP_EEPROM_MAX_ADDR 8191
#endif
// External flash configuration
#ifndef EXTERNAL_FLASH_SPI_SLAVE_SELECT_PIN
# define EXTERNAL_FLASH_SPI_SLAVE_SELECT_PIN PAL_LINE(GPIOB, 12)
# define EXTERNAL_FLASH_SPI_CLOCK_DIVISOR 2 // 48MHz; max supported by W25Q128JV is 133MHz
# define EXTERNAL_FLASH_BYTE_COUNT (16 * 1024 * 1024) //128Mbit or 16MByte
# define EXTERNAL_FLASH_PAGE_SIZE 256
# define EXTERNAL_FLASH_SPI_TIMEOUT 200000 //datasheet max is 200 seconds for flash chip erase
#endif
// SPI Configuration (needed for FRAM and FLASH)
#ifndef SPI_DRIVER
# define SPI_DRIVER SPID1
#endif
#ifndef SPI_SCK_PIN
# define SPI_SCK_PIN PAL_LINE(GPIOB, 3)
#endif
#ifndef SPI_MOSI_PIN
# define SPI_MOSI_PIN PAL_LINE(GPIOB, 5)
#endif
#ifndef SPI_MISO_PIN
# define SPI_MISO_PIN PAL_LINE(GPIOB, 4)
#endif
// I2C Configuration
#ifdef CONVERT_TO_BONSAI_C4
# ifndef I2C1_SCL_PIN
# define I2C1_SCL_PIN PAL_LINE(GPIOB, 6)
# endif
# ifndef I2C1_SDA_PIN
# define I2C1_SDA_PIN PAL_LINE(GPIOB, 9)
# endif
#endif
// WS2812-style LED control on pin A10
#ifdef WS2812_DRIVER_PWM
# ifndef WS2812_DI_PIN
# define WS2812_DI_PIN PAL_LINE(GPIOA, 10)
# endif
# ifndef WS2812_PWM_DRIVER
# define WS2812_PWM_DRIVER PWMD1
# endif
# ifndef WS2812_PWM_CHANNEL
# define WS2812_PWM_CHANNEL 3
# endif
# ifndef WS2812_PWM_PAL_MODE
# define WS2812_PWM_PAL_MODE 1
# endif
# ifndef WS2812_DMA_STREAM
# define WS2812_DMA_STREAM STM32_DMA2_STREAM5
# endif
# ifndef WS2812_DMA_CHANNEL
# define WS2812_DMA_CHANNEL 6
# endif
#endif
#ifndef USB_VBUS_PIN
# define USB_VBUS_PIN PAL_LINE(GPIOA, 9)
#endif

49
platforms/chibios/boards/BONSAI_C4/configs/halconf.h
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/* Copyright 2022 David Hoelscher, customMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef HAL_USE_SPI
# define HAL_USE_SPI TRUE
#endif
#ifndef HAL_USE_I2C
# define HAL_USE_I2C TRUE
#endif
#ifdef SPLIT_KEYBOARD
# ifndef HAL_USE_SERIAL
# define HAL_USE_SERIAL TRUE
# endif
# ifndef SERIAL_BUFFERS_SIZE
# define SERIAL_BUFFERS_SIZE 256
# endif
#endif
#ifdef WS2812_DRIVER_PWM
# ifndef HAL_USE_PWM
# define HAL_USE_PWM TRUE
# endif
#endif
#ifndef SPI_SELECT_MODE
# define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
#ifndef SPI_USE_WAIT
# define SPI_USE_WAIT TRUE
#endif
#include_next <halconf.h>

252
platforms/chibios/boards/BONSAI_C4/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F411_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 96
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 TRUE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 TRUE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_PROMICRO_RP2040/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/RP_PICO_RP2040/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/RP_PICO_RP2040
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

12
platforms/chibios/boards/GENERIC_PROMICRO_RP2040/configs/board.h
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// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include_next <board.h>
#undef BOARD_RP_PICO_RP2040
#define BOARD_GENERIC_PROMICRO_RP2040
#undef BOARD_NAME
#define BOARD_NAME "Pro Micro RP2040"

13
platforms/chibios/boards/GENERIC_PROMICRO_RP2040/configs/chconf.h
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// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define CH_CFG_SMP_MODE TRUE
#define CH_CFG_ST_RESOLUTION 32
#define CH_CFG_ST_FREQUENCY 1000000
#define CH_CFG_INTERVALS_SIZE 32
#define CH_CFG_TIME_TYPES_SIZE 32
#define CH_CFG_ST_TIMEDELTA 20
#include_next <chconf.h>

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platforms/chibios/boards/GENERIC_PROMICRO_RP2040/configs/config.h
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// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
/**======================
** I2C Driver
*========================**/
#if !defined(I2C_DRIVER)
# define I2C_DRIVER I2CD1
#endif
#if !defined(I2C1_SDA_PIN)
# define I2C1_SDA_PIN GP2
#endif
#if !defined(I2C1_SCL_PIN)
# define I2C1_SCL_PIN GP3
#endif
/**======================
** SPI Driver
*========================**/
#if !defined(SPI_DRIVER)
# define SPI_DRIVER SPID0
#endif
#if !defined(SPI_SCK_PIN)
# define SPI_SCK_PIN GP18
#endif
#if !defined(SPI_MISO_PIN)
# define SPI_MISO_PIN GP20
#endif
#if !defined(SPI_MOSI_PIN)
# define SPI_MOSI_PIN GP19
#endif
/**======================
** SERIAL Driver
*========================**/
#if !defined(SERIAL_USART_DRIVER)
# define SERIAL_USART_DRIVER SIOD0
#endif
#if !defined(SERIAL_USART_TX_PIN) && !defined(SOFT_SERIAL_PIN)
# define SERIAL_USART_TX_PIN GP0
#endif
#if !defined(SERIAL_USART_RX_PIN)
# define SERIAL_USART_RX_PIN GP1
#endif
/**======================
** Double-tap
*========================**/
#define RP2040_BOOTLOADER_DOUBLE_TAP_RESET

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/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* RP2040_MCUCONF drivers configuration.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...1 Lowest...Highest.
*/
#define RP2040_MCUCONF
/*
* HAL driver system settings.
*/
#define RP_NO_INIT FALSE
#define RP_CORE1_START FALSE
#define RP_CORE1_VECTORS_TABLE _vectors
#define RP_CORE1_ENTRY_POINT _crt0_c1_entry
#define RP_CORE1_STACK_END __c1_main_stack_end__
/*
* IRQ system settings.
*/
#define RP_IRQ_SYSTICK_PRIORITY 2
#define RP_IRQ_TIMER_ALARM0_PRIORITY 2
#define RP_IRQ_TIMER_ALARM1_PRIORITY 2
#define RP_IRQ_TIMER_ALARM2_PRIORITY 2
#define RP_IRQ_TIMER_ALARM3_PRIORITY 2
#define RP_IRQ_ADC1_PRIORITY 3
#define RP_IRQ_UART0_PRIORITY 3
#define RP_IRQ_UART1_PRIORITY 3
#define RP_IRQ_SPI0_PRIORITY 2
#define RP_IRQ_SPI1_PRIORITY 2
#define RP_IRQ_USB0_PRIORITY 3
#define RP_IRQ_I2C0_PRIORITY 2
#define RP_IRQ_I2C1_PRIORITY 2
/*
* ADC driver system settings.
*/
#define RP_ADC_USE_ADC1 TRUE
/*
* SIO driver system settings.
*/
#define RP_SIO_USE_UART0 TRUE
#define RP_SIO_USE_UART1 FALSE
/*
* SPI driver system settings.
*/
#define RP_SPI_USE_SPI0 TRUE
#define RP_SPI_USE_SPI1 FALSE
#define RP_SPI_SPI0_RX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI0_TX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI1_RX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI1_TX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI0_DMA_PRIORITY 1
#define RP_SPI_SPI1_DMA_PRIORITY 1
#define RP_SPI_DMA_ERROR_HOOK(spip)
/*
* PWM driver system settings.
*/
#define RP_PWM_USE_PWM0 FALSE
#define RP_PWM_USE_PWM1 FALSE
#define RP_PWM_USE_PWM2 FALSE
#define RP_PWM_USE_PWM3 FALSE
#define RP_PWM_USE_PWM4 FALSE
#define RP_PWM_USE_PWM5 FALSE
#define RP_PWM_USE_PWM6 FALSE
#define RP_PWM_USE_PWM7 FALSE
#define RP_PWM_IRQ_WRAP_NUMBER_PRIORITY 3
/*
* I2C driver system settings.
*/
#define RP_I2C_USE_I2C0 FALSE
#define RP_I2C_USE_I2C1 TRUE
#define RP_I2C_BUSY_TIMEOUT 50
#define RP_I2C_ADDRESS_MODE_10BIT FALSE
/*
* USB driver system settings.
*/
#define RP_USB_USE_USBD0 TRUE
#define RP_USB_FORCE_VBUS_DETECT TRUE
#define RP_USE_EXTERNAL_VBUS_DETECT FALSE
#define RP_USB_USE_ERROR_DATA_SEQ_INTR FALSE
#endif /* MCUCONF_H */

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platforms/chibios/boards/GENERIC_RP_RP2040/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/RP_PICO_RP2040/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/RP_PICO_RP2040
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

12
platforms/chibios/boards/GENERIC_RP_RP2040/configs/board.h
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// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include_next <board.h>
#undef BOARD_RP_PICO_RP2040
#define BOARD_GENERIC_RP2040
#undef BOARD_NAME
#define BOARD_NAME "Generic Raspberry Pi RP2040"

13
platforms/chibios/boards/GENERIC_RP_RP2040/configs/chconf.h
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// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define CH_CFG_SMP_MODE TRUE
#define CH_CFG_ST_RESOLUTION 32
#define CH_CFG_ST_FREQUENCY 1000000
#define CH_CFG_INTERVALS_SIZE 32
#define CH_CFG_TIME_TYPES_SIZE 32
#define CH_CFG_ST_TIMEDELTA 20
#include_next <chconf.h>

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platforms/chibios/boards/GENERIC_RP_RP2040/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* RP2040_MCUCONF drivers configuration.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...1 Lowest...Highest.
*/
#define RP2040_MCUCONF
/*
* HAL driver system settings.
*/
#define RP_NO_INIT FALSE
#define RP_CORE1_START FALSE
#define RP_CORE1_VECTORS_TABLE _vectors
#define RP_CORE1_ENTRY_POINT _crt0_c1_entry
#define RP_CORE1_STACK_END __c1_main_stack_end__
/*
* IRQ system settings.
*/
#define RP_IRQ_SYSTICK_PRIORITY 2
#define RP_IRQ_TIMER_ALARM0_PRIORITY 2
#define RP_IRQ_TIMER_ALARM1_PRIORITY 2
#define RP_IRQ_TIMER_ALARM2_PRIORITY 2
#define RP_IRQ_TIMER_ALARM3_PRIORITY 2
#define RP_IRQ_ADC1_PRIORITY 3
#define RP_IRQ_UART0_PRIORITY 3
#define RP_IRQ_UART1_PRIORITY 3
#define RP_IRQ_SPI0_PRIORITY 2
#define RP_IRQ_SPI1_PRIORITY 2
#define RP_IRQ_USB0_PRIORITY 3
#define RP_IRQ_I2C0_PRIORITY 2
#define RP_IRQ_I2C1_PRIORITY 2
/*
* ADC driver system settings.
*/
#define RP_ADC_USE_ADC1 FALSE
/*
* SIO driver system settings.
*/
#define RP_SIO_USE_UART0 FALSE
#define RP_SIO_USE_UART1 FALSE
/*
* SPI driver system settings.
*/
#define RP_SPI_USE_SPI0 FALSE
#define RP_SPI_USE_SPI1 FALSE
#define RP_SPI_SPI0_RX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI0_TX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI1_RX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI1_TX_DMA_CHANNEL RP_DMA_CHANNEL_ID_ANY
#define RP_SPI_SPI0_DMA_PRIORITY 1
#define RP_SPI_SPI1_DMA_PRIORITY 1
#define RP_SPI_DMA_ERROR_HOOK(spip)
/*
* PWM driver system settings.
*/
#define RP_PWM_USE_PWM0 FALSE
#define RP_PWM_USE_PWM1 FALSE
#define RP_PWM_USE_PWM2 FALSE
#define RP_PWM_USE_PWM3 FALSE
#define RP_PWM_USE_PWM4 FALSE
#define RP_PWM_USE_PWM5 FALSE
#define RP_PWM_USE_PWM6 FALSE
#define RP_PWM_USE_PWM7 FALSE
#define RP_PWM_IRQ_WRAP_NUMBER_PRIORITY 3
/*
* I2C driver system settings.
*/
#define RP_I2C_USE_I2C0 FALSE
#define RP_I2C_USE_I2C1 FALSE
#define RP_I2C_BUSY_TIMEOUT 50
#define RP_I2C_ADDRESS_MODE_10BIT FALSE
/*
* USB driver system settings.
*/
#define RP_USB_USE_USBD0 TRUE
#define RP_USB_FORCE_VBUS_DETECT TRUE
#define RP_USE_EXTERNAL_VBUS_DETECT FALSE
#define RP_USB_USE_ERROR_DATA_SEQ_INTR FALSE
#endif /* MCUCONF_H */

265
platforms/chibios/boards/GENERIC_STM32_F042X6/board/board.c
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include <hal.h>
#include <stm32_gpio.h>
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB(STM32_GPIO_EN_MASK);
rccEnableAHB(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

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platforms/chibios/boards/GENERIC_STM32_F042X6/board/board.h
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H
#define _BOARD_H
/*
* Setup for STMicroelectronics STM32 Nucleo32-F042K6 board.
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_STM32_F042X6
#define BOARD_NAME "Generic STM32F042 PCB"
/*
* Board oscillators-related settings.
* NOTE: LSE not fitted.
* NOTE: HSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0U
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 0U
#endif
/*
* MCU type as defined in the ST header.
*/
#define STM32F042x6
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN0 0U
#define GPIOD_PIN1 1U
#define GPIOD_PIN2 2U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOE_PIN0 0U
#define GPIOE_PIN1 1U
#define GPIOE_PIN2 2U
#define GPIOE_PIN3 3U
#define GPIOE_PIN4 4U
#define GPIOE_PIN5 5U
#define GPIOE_PIN6 6U
#define GPIOE_PIN7 7U
#define GPIOE_PIN8 8U
#define GPIOE_PIN9 9U
#define GPIOE_PIN10 10U
#define GPIOE_PIN11 11U
#define GPIOE_PIN12 12U
#define GPIOE_PIN13 13U
#define GPIOE_PIN14 14U
#define GPIOE_PIN15 15U
#define GPIOF_PIN0 0U
#define GPIOF_PIN1 1U
#define GPIOF_PIN2 2U
#define GPIOF_PIN3 3U
#define GPIOF_PIN4 4U
#define GPIOF_PIN5 5U
#define GPIOF_PIN6 6U
#define GPIOF_PIN7 7U
#define GPIOF_PIN8 8U
#define GPIOF_PIN9 9U
#define GPIOF_PIN10 10U
#define GPIOF_PIN11 11U
#define GPIOF_PIN12 12U
#define GPIOF_PIN13 13U
#define GPIOF_PIN14 14U
#define GPIOF_PIN15 15U
/*
* IO lines assignments.
*/
#define LINE_BOOT0 PAL_LINE(GPIOB, 8U)
#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - COL5
* PA1 - COL4
* PA2 - COL3
* PA3 - COL2
* PA4 - COL1
* PA5 - COL0
* PA6 - ROW4
* PA7 - ROW3
* PA8 - NC
* PA9 - ROW1
* PA10 - ROW0
* PA11 - USB_DM
* PA12 - USB_DP
* PA13 - COL15/SWDIO (for now, COL15)
* PA14 - COL14/SWCLK (for now, COL14)
* PA15 - COL13
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
PIN_MODE_INPUT(GPIOA_PIN1) | \
PIN_MODE_INPUT(GPIOA_PIN2) | \
PIN_MODE_INPUT(GPIOA_PIN3) | \
PIN_MODE_INPUT(GPIOA_PIN4) | \
PIN_MODE_INPUT(GPIOA_PIN5) | \
PIN_MODE_INPUT(GPIOA_PIN6) | \
PIN_MODE_INPUT(GPIOA_PIN7) | \
PIN_MODE_INPUT(GPIOA_PIN8) | \
PIN_MODE_INPUT(GPIOA_PIN9) | \
PIN_MODE_INPUT(GPIOA_PIN10) | \
PIN_MODE_INPUT(GPIOA_PIN11) | \
PIN_MODE_INPUT(GPIOA_PIN12) | \
PIN_MODE_INPUT(GPIOA_PIN13) | \
PIN_MODE_INPUT(GPIOA_PIN14) | \
PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
PIN_OSPEED_HIGH(GPIOA_PIN11) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN13) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN14) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
PIN_PUPDR_PULLUP(GPIOA_PIN13) | \
PIN_PUPDR_PULLUP(GPIOA_PIN14) | \
PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
PIN_ODR_HIGH(GPIOA_PIN1) | \
PIN_ODR_HIGH(GPIOA_PIN2) | \
PIN_ODR_HIGH(GPIOA_PIN3) | \
PIN_ODR_HIGH(GPIOA_PIN4) | \
PIN_ODR_HIGH(GPIOA_PIN5) | \
PIN_ODR_HIGH(GPIOA_PIN6) | \
PIN_ODR_HIGH(GPIOA_PIN7) | \
PIN_ODR_HIGH(GPIOA_PIN8) | \
PIN_ODR_HIGH(GPIOA_PIN9) | \
PIN_ODR_HIGH(GPIOA_PIN10) | \
PIN_ODR_HIGH(GPIOA_PIN11) | \
PIN_ODR_HIGH(GPIOA_PIN12) | \
PIN_ODR_HIGH(GPIOA_PIN13) | \
PIN_ODR_HIGH(GPIOA_PIN14) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
PIN_AFIO_AF(GPIOA_PIN7, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
PIN_AFIO_AF(GPIOA_PIN13, 0U) | \
PIN_AFIO_AF(GPIOA_PIN14, 0U) | \
PIN_AFIO_AF(GPIOA_PIN15, 0U))
/*
* GPIOB setup:
*
* PB0 - ROW2
* PB1 - RGB_D
* PB2 - PIN2 (input pullup).
* PB3 - COL12
* PB4 - COL11
* PB5 - COL10
* PB6 - COL9
* PB7 - COL8
* PB8 - BOOT0 (set as output for STM32F042)
* PB9 - PIN9 (input pullup).
* PB10 - PIN10 (input pullup).
* PB11 - PIN11 (input pullup).
* PB12 - PIN12 (input pullup).
* PB13 - PIN13 (input pullup).
* PB14 - PIN14 (input pullup).
* PB15 - PIN15 (input pullup).
*/
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_OUTPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_INPUT(GPIOB_PIN3) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_PIN6) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_OUTPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_PIN9) | \
PIN_MODE_INPUT(GPIOB_PIN10) | \
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
PIN_OSPEED_HIGH(GPIOB_PIN1) | \
PIN_OSPEED_HIGH(GPIOB_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN3) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
PIN_OSPEED_HIGH(GPIOB_PIN9) | \
PIN_OSPEED_HIGH(GPIOB_PIN10) | \
PIN_OSPEED_HIGH(GPIOB_PIN11) | \
PIN_OSPEED_HIGH(GPIOB_PIN12) | \
PIN_OSPEED_HIGH(GPIOB_PIN13) | \
PIN_OSPEED_HIGH(GPIOB_PIN14) | \
PIN_OSPEED_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
PIN_ODR_HIGH(GPIOB_PIN1) | \
PIN_ODR_HIGH(GPIOB_PIN2) | \
PIN_ODR_HIGH(GPIOB_PIN3) | \
PIN_ODR_HIGH(GPIOB_PIN4) | \
PIN_ODR_HIGH(GPIOB_PIN5) | \
PIN_ODR_HIGH(GPIOB_PIN6) | \
PIN_ODR_HIGH(GPIOB_PIN7) | \
PIN_ODR_HIGH(GPIOB_PIN8) | \
PIN_ODR_HIGH(GPIOB_PIN9) | \
PIN_ODR_HIGH(GPIOB_PIN10) | \
PIN_ODR_HIGH(GPIOB_PIN11) | \
PIN_ODR_HIGH(GPIOB_PIN12) | \
PIN_ODR_HIGH(GPIOB_PIN13) | \
PIN_ODR_HIGH(GPIOB_PIN14) | \
PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_PIN3, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
/*
* GPIOC setup:
*
* PC0 - PIN0 (input pullup).
* PC1 - PIN1 (input pullup).
* PC2 - PIN2 (input pullup).
* PC3 - PIN3 (input pullup).
* PC4 - PIN4 (input pullup).
* PC5 - PIN5 (input pullup).
* PC6 - PIN6 (input pullup).
* PC7 - PIN7 (input pullup).
* PC8 - PIN8 (input pullup).
* PC9 - PIN9 (input pullup).
* PC10 - PIN10 (input pullup).
* PC11 - PIN11 (input pullup).
* PC12 - PIN12 (input pullup).
* PC13 - PIN13 (input pullup).
* PC14 - PIN14 (input pullup).
* PC15 - PIN15 (input pullup).
*/
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
PIN_MODE_INPUT(GPIOC_PIN1) | \
PIN_MODE_INPUT(GPIOC_PIN2) | \
PIN_MODE_INPUT(GPIOC_PIN3) | \
PIN_MODE_INPUT(GPIOC_PIN4) | \
PIN_MODE_INPUT(GPIOC_PIN5) | \
PIN_MODE_INPUT(GPIOC_PIN6) | \
PIN_MODE_INPUT(GPIOC_PIN7) | \
PIN_MODE_INPUT(GPIOC_PIN8) | \
PIN_MODE_INPUT(GPIOC_PIN9) | \
PIN_MODE_INPUT(GPIOC_PIN10) | \
PIN_MODE_INPUT(GPIOC_PIN11) | \
PIN_MODE_INPUT(GPIOC_PIN12) | \
PIN_MODE_INPUT(GPIOC_PIN13) | \
PIN_MODE_INPUT(GPIOC_PIN14) | \
PIN_MODE_INPUT(GPIOC_PIN15))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \
PIN_OSPEED_HIGH(GPIOC_PIN1) | \
PIN_OSPEED_HIGH(GPIOC_PIN2) | \
PIN_OSPEED_HIGH(GPIOC_PIN3) | \
PIN_OSPEED_HIGH(GPIOC_PIN4) | \
PIN_OSPEED_HIGH(GPIOC_PIN5) | \
PIN_OSPEED_HIGH(GPIOC_PIN6) | \
PIN_OSPEED_HIGH(GPIOC_PIN7) | \
PIN_OSPEED_HIGH(GPIOC_PIN8) | \
PIN_OSPEED_HIGH(GPIOC_PIN9) | \
PIN_OSPEED_HIGH(GPIOC_PIN10) | \
PIN_OSPEED_HIGH(GPIOC_PIN11) | \
PIN_OSPEED_HIGH(GPIOC_PIN12) | \
PIN_OSPEED_HIGH(GPIOC_PIN13) | \
PIN_OSPEED_HIGH(GPIOC_PIN14) | \
PIN_OSPEED_HIGH(GPIOC_PIN15))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
PIN_PUPDR_PULLUP(GPIOC_PIN15))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
PIN_ODR_HIGH(GPIOC_PIN1) | \
PIN_ODR_HIGH(GPIOC_PIN2) | \
PIN_ODR_HIGH(GPIOC_PIN3) | \
PIN_ODR_HIGH(GPIOC_PIN4) | \
PIN_ODR_HIGH(GPIOC_PIN5) | \
PIN_ODR_HIGH(GPIOC_PIN6) | \
PIN_ODR_HIGH(GPIOC_PIN7) | \
PIN_ODR_HIGH(GPIOC_PIN8) | \
PIN_ODR_HIGH(GPIOC_PIN9) | \
PIN_ODR_HIGH(GPIOC_PIN10) | \
PIN_ODR_HIGH(GPIOC_PIN11) | \
PIN_ODR_HIGH(GPIOC_PIN12) | \
PIN_ODR_HIGH(GPIOC_PIN13) | \
PIN_ODR_HIGH(GPIOC_PIN14) | \
PIN_ODR_HIGH(GPIOC_PIN15))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
PIN_AFIO_AF(GPIOC_PIN7, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \
PIN_AFIO_AF(GPIOC_PIN14, 0U) | \
PIN_AFIO_AF(GPIOC_PIN15, 0U))
/*
* GPIOD setup:
*
* PD0 - PIN0 (input pullup).
* PD1 - PIN1 (input pullup).
* PD2 - PIN2 (input pullup).
* PD3 - PIN3 (input pullup).
* PD4 - PIN4 (input pullup).
* PD5 - PIN5 (input pullup).
* PD6 - PIN6 (input pullup).
* PD7 - PIN7 (input pullup).
* PD8 - PIN8 (input pullup).
* PD9 - PIN9 (input pullup).
* PD10 - PIN10 (input pullup).
* PD11 - PIN11 (input pullup).
* PD12 - PIN12 (input pullup).
* PD13 - PIN13 (input pullup).
* PD14 - PIN14 (input pullup).
* PD15 - PIN15 (input pullup).
*/
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
PIN_MODE_INPUT(GPIOD_PIN1) | \
PIN_MODE_INPUT(GPIOD_PIN2) | \
PIN_MODE_INPUT(GPIOD_PIN3) | \
PIN_MODE_INPUT(GPIOD_PIN4) | \
PIN_MODE_INPUT(GPIOD_PIN5) | \
PIN_MODE_INPUT(GPIOD_PIN6) | \
PIN_MODE_INPUT(GPIOD_PIN7) | \
PIN_MODE_INPUT(GPIOD_PIN8) | \
PIN_MODE_INPUT(GPIOD_PIN9) | \
PIN_MODE_INPUT(GPIOD_PIN10) | \
PIN_MODE_INPUT(GPIOD_PIN11) | \
PIN_MODE_INPUT(GPIOD_PIN12) | \
PIN_MODE_INPUT(GPIOD_PIN13) | \
PIN_MODE_INPUT(GPIOD_PIN14) | \
PIN_MODE_INPUT(GPIOD_PIN15))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
PIN_OSPEED_HIGH(GPIOD_PIN1) | \
PIN_OSPEED_HIGH(GPIOD_PIN2) | \
PIN_OSPEED_HIGH(GPIOD_PIN3) | \
PIN_OSPEED_HIGH(GPIOD_PIN4) | \
PIN_OSPEED_HIGH(GPIOD_PIN5) | \
PIN_OSPEED_HIGH(GPIOD_PIN6) | \
PIN_OSPEED_HIGH(GPIOD_PIN7) | \
PIN_OSPEED_HIGH(GPIOD_PIN8) | \
PIN_OSPEED_HIGH(GPIOD_PIN9) | \
PIN_OSPEED_HIGH(GPIOD_PIN10) | \
PIN_OSPEED_HIGH(GPIOD_PIN11) | \
PIN_OSPEED_HIGH(GPIOD_PIN12) | \
PIN_OSPEED_HIGH(GPIOD_PIN13) | \
PIN_OSPEED_HIGH(GPIOD_PIN14) | \
PIN_OSPEED_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
PIN_PUPDR_PULLUP(GPIOD_PIN15))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
PIN_ODR_HIGH(GPIOD_PIN1) | \
PIN_ODR_HIGH(GPIOD_PIN2) | \
PIN_ODR_HIGH(GPIOD_PIN3) | \
PIN_ODR_HIGH(GPIOD_PIN4) | \
PIN_ODR_HIGH(GPIOD_PIN5) | \
PIN_ODR_HIGH(GPIOD_PIN6) | \
PIN_ODR_HIGH(GPIOD_PIN7) | \
PIN_ODR_HIGH(GPIOD_PIN8) | \
PIN_ODR_HIGH(GPIOD_PIN9) | \
PIN_ODR_HIGH(GPIOD_PIN10) | \
PIN_ODR_HIGH(GPIOD_PIN11) | \
PIN_ODR_HIGH(GPIOD_PIN12) | \
PIN_ODR_HIGH(GPIOD_PIN13) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
*
* PE0 - PIN0 (input pullup).
* PE1 - PIN1 (input pullup).
* PE2 - PIN2 (input pullup).
* PE3 - PIN3 (input pullup).
* PE4 - PIN4 (input pullup).
* PE5 - PIN5 (input pullup).
* PE6 - PIN6 (input pullup).
* PE7 - PIN7 (input pullup).
* PE8 - PIN8 (input pullup).
* PE9 - PIN9 (input pullup).
* PE10 - PIN10 (input pullup).
* PE11 - PIN11 (input pullup).
* PE12 - PIN12 (input pullup).
* PE13 - PIN13 (input pullup).
* PE14 - PIN14 (input pullup).
* PE15 - PIN15 (input pullup).
*/
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
PIN_MODE_INPUT(GPIOE_PIN1) | \
PIN_MODE_INPUT(GPIOE_PIN2) | \
PIN_MODE_INPUT(GPIOE_PIN3) | \
PIN_MODE_INPUT(GPIOE_PIN4) | \
PIN_MODE_INPUT(GPIOE_PIN5) | \
PIN_MODE_INPUT(GPIOE_PIN6) | \
PIN_MODE_INPUT(GPIOE_PIN7) | \
PIN_MODE_INPUT(GPIOE_PIN8) | \
PIN_MODE_INPUT(GPIOE_PIN9) | \
PIN_MODE_INPUT(GPIOE_PIN10) | \
PIN_MODE_INPUT(GPIOE_PIN11) | \
PIN_MODE_INPUT(GPIOE_PIN12) | \
PIN_MODE_INPUT(GPIOE_PIN13) | \
PIN_MODE_INPUT(GPIOE_PIN14) | \
PIN_MODE_INPUT(GPIOE_PIN15))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
PIN_OSPEED_HIGH(GPIOE_PIN1) | \
PIN_OSPEED_HIGH(GPIOE_PIN2) | \
PIN_OSPEED_HIGH(GPIOE_PIN3) | \
PIN_OSPEED_HIGH(GPIOE_PIN4) | \
PIN_OSPEED_HIGH(GPIOE_PIN5) | \
PIN_OSPEED_HIGH(GPIOE_PIN6) | \
PIN_OSPEED_HIGH(GPIOE_PIN7) | \
PIN_OSPEED_HIGH(GPIOE_PIN8) | \
PIN_OSPEED_HIGH(GPIOE_PIN9) | \
PIN_OSPEED_HIGH(GPIOE_PIN10) | \
PIN_OSPEED_HIGH(GPIOE_PIN11) | \
PIN_OSPEED_HIGH(GPIOE_PIN12) | \
PIN_OSPEED_HIGH(GPIOE_PIN13) | \
PIN_OSPEED_HIGH(GPIOE_PIN14) | \
PIN_OSPEED_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
PIN_PUPDR_PULLUP(GPIOE_PIN15))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
PIN_ODR_HIGH(GPIOE_PIN1) | \
PIN_ODR_HIGH(GPIOE_PIN2) | \
PIN_ODR_HIGH(GPIOE_PIN3) | \
PIN_ODR_HIGH(GPIOE_PIN4) | \
PIN_ODR_HIGH(GPIOE_PIN5) | \
PIN_ODR_HIGH(GPIOE_PIN6) | \
PIN_ODR_HIGH(GPIOE_PIN7) | \
PIN_ODR_HIGH(GPIOE_PIN8) | \
PIN_ODR_HIGH(GPIOE_PIN9) | \
PIN_ODR_HIGH(GPIOE_PIN10) | \
PIN_ODR_HIGH(GPIOE_PIN11) | \
PIN_ODR_HIGH(GPIOE_PIN12) | \
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
*
* PF0 - COL7
* PF1 - COL6
* PF2 - PIN2 (input pullup).
* PF3 - PIN3 (input pullup).
* PF4 - PIN4 (input pullup).
* PF5 - PIN5 (input pullup).
* PF6 - PIN6 (input pullup).
* PF7 - PIN7 (input pullup).
* PF8 - PIN8 (input pullup).
* PF9 - PIN9 (input pullup).
* PF10 - PIN10 (input pullup).
* PF11 - PIN11 (input pullup).
* PF12 - PIN12 (input pullup).
* PF13 - PIN13 (input pullup).
* PF14 - PIN14 (input pullup).
* PF15 - PIN15 (input pullup).
*/
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
PIN_MODE_INPUT(GPIOF_PIN1) | \
PIN_MODE_INPUT(GPIOF_PIN2) | \
PIN_MODE_INPUT(GPIOF_PIN3) | \
PIN_MODE_INPUT(GPIOF_PIN4) | \
PIN_MODE_INPUT(GPIOF_PIN5) | \
PIN_MODE_INPUT(GPIOF_PIN6) | \
PIN_MODE_INPUT(GPIOF_PIN7) | \
PIN_MODE_INPUT(GPIOF_PIN8) | \
PIN_MODE_INPUT(GPIOF_PIN9) | \
PIN_MODE_INPUT(GPIOF_PIN10) | \
PIN_MODE_INPUT(GPIOF_PIN11) | \
PIN_MODE_INPUT(GPIOF_PIN12) | \
PIN_MODE_INPUT(GPIOF_PIN13) | \
PIN_MODE_INPUT(GPIOF_PIN14) | \
PIN_MODE_INPUT(GPIOF_PIN15))
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
PIN_OSPEED_HIGH(GPIOF_PIN2) | \
PIN_OSPEED_HIGH(GPIOF_PIN3) | \
PIN_OSPEED_HIGH(GPIOF_PIN4) | \
PIN_OSPEED_HIGH(GPIOF_PIN5) | \
PIN_OSPEED_HIGH(GPIOF_PIN6) | \
PIN_OSPEED_HIGH(GPIOF_PIN7) | \
PIN_OSPEED_HIGH(GPIOF_PIN8) | \
PIN_OSPEED_HIGH(GPIOF_PIN9) | \
PIN_OSPEED_HIGH(GPIOF_PIN10) | \
PIN_OSPEED_HIGH(GPIOF_PIN11) | \
PIN_OSPEED_HIGH(GPIOF_PIN12) | \
PIN_OSPEED_HIGH(GPIOF_PIN13) | \
PIN_OSPEED_HIGH(GPIOF_PIN14) | \
PIN_OSPEED_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
PIN_PUPDR_PULLUP(GPIOF_PIN15))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
PIN_ODR_HIGH(GPIOF_PIN1) | \
PIN_ODR_HIGH(GPIOF_PIN2) | \
PIN_ODR_HIGH(GPIOF_PIN3) | \
PIN_ODR_HIGH(GPIOF_PIN4) | \
PIN_ODR_HIGH(GPIOF_PIN5) | \
PIN_ODR_HIGH(GPIOF_PIN6) | \
PIN_ODR_HIGH(GPIOF_PIN7) | \
PIN_ODR_HIGH(GPIOF_PIN8) | \
PIN_ODR_HIGH(GPIOF_PIN9) | \
PIN_ODR_HIGH(GPIOF_PIN10) | \
PIN_ODR_HIGH(GPIOF_PIN11) | \
PIN_ODR_HIGH(GPIOF_PIN12) | \
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H */

9
platforms/chibios/boards/GENERIC_STM32_F042X6/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/GENERIC_STM32_F042X6/configs/config.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

168
platforms/chibios/boards/GENERIC_STM32_F042X6/configs/mcuconf.h
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@ -1,168 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F0xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
#define STM32_GPT_TIM3_IRQ_PRIORITY 2
#define STM32_GPT_TIM14_IRQ_PRIORITY 2
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 3
#define STM32_ICU_TIM2_IRQ_PRIORITY 3
#define STM32_ICU_TIM3_IRQ_PRIORITY 3
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 3
#define STM32_PWM_TIM2_IRQ_PRIORITY 3
#define STM32_PWM_TIM3_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 2
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 3
#define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
#endif /* _MCUCONF_H_ */

9
platforms/chibios/boards/GENERIC_STM32_F072XB/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F072RB/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F072RB
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/GENERIC_STM32_F072XB/configs/board.h
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@ -1,20 +0,0 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSE_BYPASS

20
platforms/chibios/boards/GENERIC_STM32_F072XB/configs/config.h
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@ -1,20 +0,0 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

180
platforms/chibios/boards/GENERIC_STM32_F072XB/configs/mcuconf.h
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@ -1,180 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F0xx_MCUCONF
// #define STM32F070xB
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
#define STM32_GPT_TIM3_IRQ_PRIORITY 2
#define STM32_GPT_TIM14_IRQ_PRIORITY 2
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 3
#define STM32_ICU_TIM2_IRQ_PRIORITY 3
#define STM32_ICU_TIM3_IRQ_PRIORITY 3
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 3
#define STM32_PWM_TIM2_IRQ_PRIORITY 3
#define STM32_PWM_TIM3_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 2
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 3
#define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
#endif /* _MCUCONF_H_ */

9
platforms/chibios/boards/GENERIC_STM32_F303XC/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

37
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSE_BYPASS
/*
* USB bus activation macro, required by the USB driver.
*/
#define usb_lld_connect_bus(usbp) \
do { \
palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_ALTERNATE(14)); \
} while (0)
/*
* USB bus de-activation macro, required by the USB driver.
*/
#define usb_lld_disconnect_bus(usbp) \
do { \
palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_OUTPUT_PUSHPULL); \
palClearPad(GPIOA, GPIOA_USB_DP); \
} while (0)

20
platforms/chibios/boards/GENERIC_STM32_F303XC/configs/config.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F3xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F3xx_MCUCONF
#define STM32F303_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_USART2SW STM32_USART2SW_PCLK
#define STM32_USART3SW STM32_USART3SW_PCLK
#define STM32_UART4SW STM32_UART4SW_PCLK
#define STM32_UART5SW STM32_UART5SW_PCLK
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 15
#define STM32_IRQ_EXTI20_PRIORITY 15
#define STM32_IRQ_EXTI21_22_29_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC4 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_F401XC/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
// Force B9 as input to align with qmk defaults
#undef VAL_GPIOB_MODER
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_INPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_ALTERNATE(GPIOB_SWO) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_INPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#undef VAL_GPIOB_PUPDR
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_SWO) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#undef VAL_GPIOB_AFRL
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_SWO, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#undef VAL_GPIOB_AFRH
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#undef STM32_HSE_BYPASS

32
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F401_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 168
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

28
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h
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@ -1,28 +0,0 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define STM32_HSECLK 12000000
// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
#define BOARD_OTG_NOVBUSSENS
#include_next <board.h>
#undef STM32_HSE_BYPASS
#undef STM32F407xx
#define STM32F405xG
#define STM32F405xx

23
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
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@ -1,23 +0,0 @@
/* Copyright 2021 Andrei Purdea
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

347
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
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@ -1,347 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F405_MCUCONF
#define STM32F415_MCUCONF
#define STM32F407_MCUCONF
#define STM32F417_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 12
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define STM32_HSECLK 8000000
// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
#define BOARD_OTG_NOVBUSSENS
#include_next <board.h>
#undef STM32_HSE_BYPASS

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/* Copyright 2021 Andrei Purdea
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F405_MCUCONF
#define STM32F415_MCUCONF
#define STM32F407_MCUCONF
#define STM32F417_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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platforms/chibios/boards/GENERIC_STM32_F411XE/configs/board.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSE_BYPASS

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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F411_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 96
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_F446XE/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

24
platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h
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@ -1,24 +0,0 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define STM32_HSECLK 16000000
// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
#define BOARD_OTG_NOVBUSSENS
#include_next <board.h>
#undef STM32_HSE_BYPASS

19
platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
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@ -1,19 +0,0 @@
/* Copyright 2021 Andrei Purdea
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

373
platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h
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@ -1,373 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F446_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 180
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SM_VALUE 8
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIM_VALUE 8
#define STM32_PLLSAIP_VALUE 8
#define STM32_PLLSAIQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSE
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
#define STM32_IRQ_UART7_PRIORITY 12
#define STM32_IRQ_UART8_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USE_UART7 FALSE
#define STM32_SERIAL_USE_UART8 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_G431XB/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

7
platforms/chibios/boards/GENERIC_STM32_G431XB/configs/config.h
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// Copyright 2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

338
platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32G4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G4xx_MCUCONF
#define STM32G431_MCUCONF
#define STM32G441_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRD (0U)
#define STM32_PWR_PDCRD (0U)
#define STM32_PWR_PUCRE (0U)
#define STM32_PWR_PDCRE (0U)
#define STM32_PWR_PUCRF (0U)
#define STM32_PWR_PDCRF (0U)
#define STM32_PWR_PUCRG (0U)
#define STM32_PWR_PDCRG (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 80
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI164041_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI212229_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_UP_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_USE_DAC3_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_TAMP_CR1_INIT 0
#define STM32_TAMP_CR2_INIT 0
#define STM32_TAMP_FLTCR_INIT 0
#define STM32_TAMP_IER_INIT 0
/*
* SDC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_USART3 FALSE
#define STM32_SIO_USE_UART4 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 5
#define STM32_USB_USB1_LP_IRQ_PRIORITY 6
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_G474XE/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

30
platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h
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/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef STM32_BOOTLOADER_DUAL_BANK
# define STM32_BOOTLOADER_DUAL_BANK FALSE
#endif
// To Enter bootloader from `RESET` keycode, you'll need to dedicate a GPIO to
// charge an RC network on the BOOT0 pin.
// See the QMK Discord's #hardware channel pins for an example circuit.
// Insert these two lines into your keyboard's `config.h` file.
// In the case below, PB7 is selected to charge.
#if 0
#define STM32_BOOTLOADER_DUAL_BANK TRUE
#define STM32_BOOTLOADER_DUAL_BANK_GPIO B7
#endif

405
platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32G4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G4xx_MCUCONF
#define STM32G473_MCUCONF
#define STM32G483_MCUCONF
#define STM32G474_MCUCONF
#define STM32G484_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRD (0U)
#define STM32_PWR_PDCRD (0U)
#define STM32_PWR_PUCRE (0U)
#define STM32_PWR_PDCRE (0U)
#define STM32_PWR_PUCRF (0U)
#define STM32_PWR_PDCRF (0U)
#define STM32_PWR_PUCRG (0U)
#define STM32_PWR_PDCRG (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 2
#define STM32_PLLN_VALUE 40
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 2
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_HSE
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI164041_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI212229_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
#define STM32_IRQ_FDCAN3_PRIORITY 10
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_UP_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_TIM20_UP_PRIORITY 7
#define STM32_IRQ_TIM20_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC4 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_FDCAN3 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_USE_DAC2_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH2 FALSE
#define STM32_DAC_USE_DAC4_CH1 FALSE
#define STM32_DAC_USE_DAC4_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_USE_TIM20 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_TAMP_CR1_INIT 0
#define STM32_TAMP_CR2_INIT 0
#define STM32_TAMP_FLTCR_INIT 0
#define STM32_TAMP_IER_INIT 0
/*
* SDC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_USART3 FALSE
#define STM32_SIO_USE_UART4 FALSE
#define STM32_SIO_USE_UART5 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 5
#define STM32_USB_USB1_LP_IRQ_PRIORITY 5
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#endif /* MCUCONF_H */

12
platforms/chibios/boards/GENERIC_STM32_H723XG/board/board.mk
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@ -1,12 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H723ZG/board.c
# Extra files
BOARDSRC += $(BOARD_PATH)/board/extra.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H723ZG
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

36
platforms/chibios/boards/GENERIC_STM32_H723XG/board/extra.c
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@ -1,36 +0,0 @@
// Copyright 2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include <hal.h>
#define BOOTLOADER_MAGIC 0xDEADBEEF
////////////////////////////////////////////////////////////////////////////////
// Different signalling for bootloader entry
// - RAM is cleared on reset, so we can't use the usual __ram0_end__ symbol.
// - Use backup registers in the RTC peripheral to store the magic value instead.
static inline void enable_backup_register_access(void) {
PWR->CR1 |= PWR_CR1_DBP;
}
static inline void disable_backup_register_access(void) {
PWR->CR1 &= ~PWR_CR1_DBP;
}
void bootloader_marker_enable(void) {
enable_backup_register_access();
RTC->BKP0R = BOOTLOADER_MAGIC;
disable_backup_register_access();
}
bool bootloader_marker_active(void) {
enable_backup_register_access();
bool ret = RTC->BKP0R == BOOTLOADER_MAGIC;
disable_backup_register_access();
return ret;
}
void bootloader_marker_disable(void) {
enable_backup_register_access();
RTC->BKP0R = 0;
disable_backup_register_access();
}

9
platforms/chibios/boards/GENERIC_STM32_H723XG/configs/config.h
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// Copyright 2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define USB_DRIVER USBD2
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

511
platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
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@ -1,511 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32H723/33/25/35 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32H7xx_MCUCONF
#define STM32H723_MCUCONF
#define STM32H733_MCUCONF
#define STM32H725_MCUCONF
#define STM32H735_MCUCONF
/*
* General settings.
*/
#define STM32_NO_INIT FALSE
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.
* Reading STM32 Reference Manual is required, settings in PWR_CR3 are
* very critical.
* Register constants are taken from the ST header.
*/
#define STM32_VOS STM32_VOS_SCALE0
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
#define STM32_PWR_CPUCR 0
/*
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_CSI_ENABLED FALSE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
/*
* PLLs static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
#define STM32_PLLCFGR_MASK ~0
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_P_ENABLED TRUE
#define STM32_PLL1_Q_ENABLED TRUE
#define STM32_PLL1_R_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
#define STM32_PLL1_DIVN_VALUE 275
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 1
#define STM32_PLL1_DIVQ_VALUE 10
#define STM32_PLL1_DIVR_VALUE 4
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE
#define STM32_PLL2_R_ENABLED TRUE
#define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
#define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 240
#define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 10
#define STM32_PLL3_DIVQ_VALUE 10
#define STM32_PLL3_DIVR_VALUE 10
/*
* Core clocks dynamic settings (can be changed at runtime).
* Reading STM32 Reference Manual is required.
*/
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSI_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
#define STM32_TIMPRE_ENABLE TRUE
#define STM32_HRTIMSEL 0
#define STM32_STOPKERWUCK 0
#define STM32_STOPWUCK 0
#define STM32_RTCPRE_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK
#define STM32_FMCSEL STM32_FMCSEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1
#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE_CK
#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1
#define STM32_RNGSEL STM32_RNGSEL_PLL1_Q_CK
#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_OCTOSPI1_PRIORITY 10
#define STM32_IRQ_OCTOSPI2_PRIORITY 10
#define STM32_IRQ_SDMMC1_PRIORITY 9
#define STM32_IRQ_SDMMC2_PRIORITY 9
#define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_TIM15_PRIORITY 7
#define STM32_IRQ_TIM16_PRIORITY 7
#define STM32_IRQ_TIM17_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
#define STM32_IRQ_UART7_PRIORITY 12
#define STM32_IRQ_UART8_PRIORITY 12
#define STM32_IRQ_UART9_PRIORITY 12
#define STM32_IRQ_USART10_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_SAMPLES_SIZE 16
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_USE_SDMMC1 FALSE
#define STM32_SDC_USE_SDMMC2 FALSE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000
#define STM32_SDC_SDMMC_READ_TIMEOUT 10000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC_PWRSAV TRUE
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USE_UART7 FALSE
#define STM32_SERIAL_USE_UART8 FALSE
#define STM32_SERIAL_USE_UART9 FALSE
#define STM32_SERIAL_USE_USART10 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_USART3 FALSE
#define STM32_SIO_USE_UART4 FALSE
#define STM32_SIO_USE_UART5 FALSE
#define STM32_SIO_USE_USART6 FALSE
#define STM32_SIO_USE_UART7 FALSE
#define STM32_SIO_USE_UART8 FALSE
#define STM32_SIO_USE_UART9 FALSE
#define STM32_SIO_USE_USART10 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USE_UART9 FALSE
#define STM32_UART_USE_USART10 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART9_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART9_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART10_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART10_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_UART7_DMA_PRIORITY 0
#define STM32_UART_UART8_DMA_PRIORITY 0
#define STM32_UART_UART9_DMA_PRIORITY 0
#define STM32_UART_USART10_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG2 TRUE
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_OCTOSPI1 FALSE
#define STM32_WSPI_USE_OCTOSPI2 FALSE
#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_SSHIFT FALSE
#define STM32_WSPI_OCTOSPI2_SSHIFT FALSE
#define STM32_WSPI_OCTOSPI1_DHQC FALSE
#define STM32_WSPI_OCTOSPI2_DHQC FALSE
#define STM32_WSPI_OCTOSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_OCTOSPI2_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_OCTOSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_MDMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_MDMA_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_MDMA_IRQ_PRIORITY 10
#define STM32_WSPI_DMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_L412XB/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h
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/* Copyright 2018-2021 Harrison Chan (@Xelus)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32L432xx
#define STM32L422xx

23
platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
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/* Copyright 2018-2021 Harrison Chan (@Xelus)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

250
platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32L4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32L4xx_MCUCONF
#define STM32L422_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 80
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 4
#define STM32_PLLR_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI1635_38_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_L432XC/board/board.mk
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# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

7
platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
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// Copyright 2021 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

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platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
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@ -1,269 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32L4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32L4xx_MCUCONF
#define STM32L432_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 10
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 2
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1N_VALUE 24
#define STM32_PLLSAI1PDIV_VALUE 0
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 2
#define STM32_PLLSAI1R_VALUE 2
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI1635_38_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#endif /* MCUCONF_H */

9
platforms/chibios/boards/GENERIC_STM32_L433XC/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

24
platforms/chibios/boards/GENERIC_STM32_L433XC/configs/board.h
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@ -1,24 +0,0 @@
/* Copyright 2018-2021 Harrison Chan (@Xelus)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32L432xx
// Pretend that we're an L443xx as the ChibiOS definitions for L4x2/L4x3 mistakenly don't enable GPIOH, I2C2, or SPI2.
// Until ChibiOS upstream is fixed, this should be kept at L443, as nothing in QMK currently utilises the crypto peripheral on the L443.
#define STM32L443xx

23
platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
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@ -1,23 +0,0 @@
/* Copyright 2018-2021 Harrison Chan (@Xelus)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

292
platforms/chibios/boards/GENERIC_STM32_L433XC/configs/mcuconf.h
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@ -1,292 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32L4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32L4xx_MCUCONF
#define STM32L443_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 10
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 2
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1N_VALUE 24
#define STM32_PLLSAI1PDIV_VALUE 0
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 2
#define STM32_PLLSAI1R_VALUE 2
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI1635_38_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDMMC drive system settings.
*/
#define STM32_SDC_USE_SDMMC1 FALSE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#endif /* MCUCONF_H */

86
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.c
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@ -1,86 +0,0 @@
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void wb32_gpio_init(void) {
#if WB32_HAS_GPIOA
rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
#endif
#if WB32_HAS_GPIOB
rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
#endif
#if WB32_HAS_GPIOC
rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
#endif
#if WB32_HAS_GPIOD
rccEnableAPB1(RCC_APB1ENR_GPIODEN);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
wb32_clock_init();
wb32_gpio_init();
}
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

59
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h
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@ -1,59 +0,0 @@
#pragma once
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup board.
*/
/*
* Board identifier.
*/
#if !(defined(WB32F3G71x9) || defined(WB32F3G71xB) || defined(WB32F3G71xC))
#define WB32F3G71x9
#endif
#if !defined(WB32F3G71xx)
#define WB32F3G71xx
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

9
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

26
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h
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@ -1,26 +0,0 @@
/* Copyright 2020 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file was auto-generated by:
* `qmk chibios-confmigrate -i platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h -r platforms/chibios/boards/common/configs/chconf.h`
*/
#pragma once
#define CH_CFG_ST_TIMEDELTA 0
#include_next <chconf.h>

22
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/config.h
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@ -1,22 +0,0 @@
/* Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#define USB_ENDPOINTS_ARE_REORDERABLE

168
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/mcuconf.h
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@ -1,168 +0,0 @@
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define WB32F3G71xx_MCUCONF TRUE
/*
* WB32F3G71 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
*/
/**
* @name Internal clock sources
* @{
*/
#define WB32_HSECLK 12000000
#define WB32_LSECLK 32768
/*
* HAL driver system settings.
*/
#define WB32_NO_INIT FALSE
#define WB32_MHSI_ENABLED TRUE
#define WB32_FHSI_ENABLED FALSE
#define WB32_LSI_ENABLED FALSE
#define WB32_HSE_ENABLED TRUE
#define WB32_LSE_ENABLED FALSE
#define WB32_PLL_ENABLED TRUE
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
#define WB32_PLLSRC WB32_PLLSRC_HSE
#define WB32_PLLDIV_VALUE 2
#define WB32_PLLMUL_VALUE 12 //The allowed range is 12,16,20,24.
#define WB32_HPRE 1
#define WB32_PPRE1 1
#define WB32_PPRE2 1
#define WB32_USBPRE WB32_USBPRE_DIV1P5
/*
* EXTI driver system settings.
*/
#define WB32_IRQ_EXTI0_PRIORITY 6
#define WB32_IRQ_EXTI1_PRIORITY 6
#define WB32_IRQ_EXTI2_PRIORITY 6
#define WB32_IRQ_EXTI3_PRIORITY 6
#define WB32_IRQ_EXTI4_PRIORITY 6
#define WB32_IRQ_EXTI5_9_PRIORITY 6
#define WB32_IRQ_EXTI10_15_PRIORITY 6
#define WB32_IRQ_EXTI16_PRIORITY 6
#define WB32_IRQ_EXTI17_PRIORITY 6
#define WB32_IRQ_EXTI18_PRIORITY 6
#define WB32_IRQ_EXTI19_PRIORITY 6
/*
* GPT driver system settings.
*/
#define WB32_TIM_MAX_CHANNELS 4
#define WB32_GPT_USE_TIM1 FALSE
#define WB32_GPT_USE_TIM2 FALSE
#define WB32_GPT_USE_TIM3 FALSE
#define WB32_GPT_USE_TIM4 FALSE
#define WB32_GPT_TIM1_IRQ_PRIORITY 7
#define WB32_GPT_TIM2_IRQ_PRIORITY 7
#define WB32_GPT_TIM3_IRQ_PRIORITY 7
#define WB32_GPT_TIM4_IRQ_PRIORITY 7
/*
* ICU driver system settings.
*/
#define WB32_ICU_USE_TIM1 FALSE
#define WB32_ICU_USE_TIM2 FALSE
#define WB32_ICU_USE_TIM3 FALSE
#define WB32_ICU_USE_TIM4 FALSE
#define WB32_ICU_TIM1_IRQ_PRIORITY 7
#define WB32_ICU_TIM2_IRQ_PRIORITY 7
#define WB32_ICU_TIM3_IRQ_PRIORITY 7
#define WB32_ICU_TIM4_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define WB32_PWM_USE_ADVANCED FALSE
#define WB32_PWM_USE_TIM1 FALSE
#define WB32_PWM_USE_TIM2 FALSE
#define WB32_PWM_USE_TIM3 FALSE
#define WB32_PWM_USE_TIM4 FALSE
#define WB32_PWM_TIM1_IRQ_PRIORITY 7
#define WB32_PWM_TIM2_IRQ_PRIORITY 7
#define WB32_PWM_TIM3_IRQ_PRIORITY 7
#define WB32_PWM_TIM4_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define WB32_I2C_USE_I2C1 FALSE
#define WB32_I2C_USE_I2C2 FALSE
#define WB32_I2C_BUSY_TIMEOUT 50
#define WB32_I2C_I2C1_IRQ_PRIORITY 5
#define WB32_I2C_I2C2_IRQ_PRIORITY 5
/*
* SERIAL driver system settings.
*/
#define WB32_SERIAL_USE_UART1 FALSE
#define WB32_SERIAL_USE_UART2 FALSE
#define WB32_SERIAL_USE_UART3 FALSE
#define WB32_SERIAL_USART1_PRIORITY 12
#define WB32_SERIAL_USART2_PRIORITY 12
#define WB32_SERIAL_USART3_PRIORITY 12
/*
* SPI driver system settings.
*/
#define WB32_SPI_USE_QSPI FALSE
#define WB32_SPI_USE_SPIM2 FALSE
#define WB32_SPI_USE_SPIS1 FALSE
#define WB32_SPI_USE_SPIS2 FALSE
#define WB32_SPI_QSPI_IRQ_PRIORITY 10
#define WB32_SPI_SPIM2_IRQ_PRIORITY 10
#define WB32_SPI_SPIS1_IRQ_PRIORITY 10
#define WB32_SPI_SPIS2_IRQ_PRIORITY 10
/*
* ST driver system settings.
*/
#define WB32_ST_IRQ_PRIORITY 8
#define WB32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define WB32_UART_USE_UART1 FALSE
#define WB32_UART_USE_UART2 FALSE
#define WB32_UART_USE_UART3 FALSE
#define WB32_UART_UART1_IRQ_PRIORITY 12
#define WB32_UART_UART2_IRQ_PRIORITY 12
#define WB32_UART_UART3_IRQ_PRIORITY 12
/*
* USB driver system settings.
*/
#define WB32_USB_USE_USB1 TRUE
#define WB32_USB_USB1_IRQ_PRIORITY 13
#define WB32_USB_HOST_WAKEUP_DURATION 10
#endif /* MCUCONF_H */

86
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.c
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@ -1,86 +0,0 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void wb32_gpio_init(void) {
#if WB32_HAS_GPIOA
rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
#endif
#if WB32_HAS_GPIOB
rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
#endif
#if WB32_HAS_GPIOC
rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
#endif
#if WB32_HAS_GPIOD
rccEnableAPB1(RCC_APB1ENR_GPIODEN);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
wb32_clock_init();
wb32_gpio_init();
}
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

59
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.h
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@ -1,59 +0,0 @@
#pragma once
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup board.
*/
/*
* Board identifier.
*/
#if !(defined(WB32FQ95x9) || defined(WB32FQ95xB) || defined(WB32FQ95xC))
#define WB32FQ95xB
#endif
#if !defined(WB32FQ95xx)
#define WB32FQ95xx
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

9
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.mk
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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

26
platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
View File

@ -1,26 +0,0 @@
/* Copyright 2020 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file was auto-generated by:
* `qmk chibios-confmigrate -i platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h -r platforms/chibios/boards/common/configs/chconf.h`
*/
#pragma once
#define CH_CFG_ST_TIMEDELTA 0
#include_next <chconf.h>

22
platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/config.h
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@ -1,22 +0,0 @@
/* Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#define USB_ENDPOINTS_ARE_REORDERABLE

168
platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/mcuconf.h
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@ -1,168 +0,0 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define WB32FQ95xx_MCUCONF TRUE
/*
* WB32FQ95 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
*/
/**
* @name Internal clock sources
* @{
*/
#define WB32_HSECLK 12000000
#define WB32_LSECLK 32768
/*
* HAL driver system settings.
*/
#define WB32_NO_INIT FALSE
#define WB32_MHSI_ENABLED TRUE
#define WB32_FHSI_ENABLED FALSE
#define WB32_LSI_ENABLED FALSE
#define WB32_HSE_ENABLED TRUE
#define WB32_LSE_ENABLED FALSE
#define WB32_PLL_ENABLED TRUE
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
#define WB32_PLLSRC WB32_PLLSRC_HSE
#define WB32_PLLDIV_VALUE 2
#define WB32_PLLMUL_VALUE 12 //The allowed range is 12,16,20,24.
#define WB32_HPRE 1
#define WB32_PPRE1 1
#define WB32_PPRE2 1
#define WB32_USBPRE WB32_USBPRE_DIV1P5
/*
* EXTI driver system settings.
*/
#define WB32_IRQ_EXTI0_PRIORITY 6
#define WB32_IRQ_EXTI1_PRIORITY 6
#define WB32_IRQ_EXTI2_PRIORITY 6
#define WB32_IRQ_EXTI3_PRIORITY 6
#define WB32_IRQ_EXTI4_PRIORITY 6
#define WB32_IRQ_EXTI5_9_PRIORITY 6
#define WB32_IRQ_EXTI10_15_PRIORITY 6
#define WB32_IRQ_EXTI16_PRIORITY 6
#define WB32_IRQ_EXTI17_PRIORITY 6
#define WB32_IRQ_EXTI18_PRIORITY 6
#define WB32_IRQ_EXTI19_PRIORITY 6
/*
* GPT driver system settings.
*/
#define WB32_TIM_MAX_CHANNELS 4
#define WB32_GPT_USE_TIM1 FALSE
#define WB32_GPT_USE_TIM2 FALSE
#define WB32_GPT_USE_TIM3 FALSE
#define WB32_GPT_USE_TIM4 FALSE
#define WB32_GPT_TIM1_IRQ_PRIORITY 7
#define WB32_GPT_TIM2_IRQ_PRIORITY 7
#define WB32_GPT_TIM3_IRQ_PRIORITY 7
#define WB32_GPT_TIM4_IRQ_PRIORITY 7
/*
* ICU driver system settings.
*/
#define WB32_ICU_USE_TIM1 FALSE
#define WB32_ICU_USE_TIM2 FALSE
#define WB32_ICU_USE_TIM3 FALSE
#define WB32_ICU_USE_TIM4 FALSE
#define WB32_ICU_TIM1_IRQ_PRIORITY 7
#define WB32_ICU_TIM2_IRQ_PRIORITY 7
#define WB32_ICU_TIM3_IRQ_PRIORITY 7
#define WB32_ICU_TIM4_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define WB32_PWM_USE_ADVANCED FALSE
#define WB32_PWM_USE_TIM1 FALSE
#define WB32_PWM_USE_TIM2 FALSE
#define WB32_PWM_USE_TIM3 FALSE
#define WB32_PWM_USE_TIM4 FALSE
#define WB32_PWM_TIM1_IRQ_PRIORITY 7
#define WB32_PWM_TIM2_IRQ_PRIORITY 7
#define WB32_PWM_TIM3_IRQ_PRIORITY 7
#define WB32_PWM_TIM4_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define WB32_I2C_USE_I2C1 FALSE
#define WB32_I2C_USE_I2C2 FALSE
#define WB32_I2C_BUSY_TIMEOUT 50
#define WB32_I2C_I2C1_IRQ_PRIORITY 5
#define WB32_I2C_I2C2_IRQ_PRIORITY 5
/*
* SERIAL driver system settings.
*/
#define WB32_SERIAL_USE_UART1 FALSE
#define WB32_SERIAL_USE_UART2 FALSE
#define WB32_SERIAL_USE_UART3 FALSE
#define WB32_SERIAL_USART1_PRIORITY 12
#define WB32_SERIAL_USART2_PRIORITY 12
#define WB32_SERIAL_USART3_PRIORITY 12
/*
* SPI driver system settings.
*/
#define WB32_SPI_USE_QSPI FALSE
#define WB32_SPI_USE_SPIM2 FALSE
#define WB32_SPI_USE_SPIS1 FALSE
#define WB32_SPI_USE_SPIS2 FALSE
#define WB32_SPI_QSPI_IRQ_PRIORITY 10
#define WB32_SPI_SPIM2_IRQ_PRIORITY 10
#define WB32_SPI_SPIS1_IRQ_PRIORITY 10
#define WB32_SPI_SPIS2_IRQ_PRIORITY 10
/*
* ST driver system settings.
*/
#define WB32_ST_IRQ_PRIORITY 8
#define WB32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define WB32_UART_USE_UART1 FALSE
#define WB32_UART_USE_UART2 FALSE
#define WB32_UART_USE_UART3 FALSE
#define WB32_UART_UART1_IRQ_PRIORITY 12
#define WB32_UART_UART2_IRQ_PRIORITY 12
#define WB32_UART_UART3_IRQ_PRIORITY 12
/*
* USB driver system settings.
*/
#define WB32_USB_USE_USB1 TRUE
#define WB32_USB_USB1_IRQ_PRIORITY 13
#define WB32_USB_HOST_WAKEUP_DURATION 10
#endif /* MCUCONF_H */

151
platforms/chibios/boards/IC_TEENSY_3_1/board/board.c
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@ -1,151 +0,0 @@
/*
ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <hal.h>
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
.ports =
{
{
/*
* PORTA setup.
*
* PTA4 - PIN33
* PTA5 - PIN24
* PTA12 - PIN3
* PTA13 - PIN4
*
* PTA18/19 crystal
* PTA0/3 SWD
*/
.port = IOPORT1,
.pads =
{
PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
},
},
{
/*
* PORTB setup.
*
* PTB0 - PIN16
* PTB1 - PIN17
* PTB2 - PIN19
* PTB3 - PIN18
* PTB16 - PIN0 - UART0_TX
* PTB17 - PIN1 - UART0_RX
* PTB18 - PIN32
* PTB19 - PIN25
*/
.port = IOPORT2,
.pads =
{
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
},
},
{
/*
* PORTC setup.
*
* PTC0 - PIN15
* PTC1 - PIN22
* PTC2 - PIN23
* PTC3 - PIN9
* PTC4 - PIN10
* PTC5 - PIN13
* PTC6 - PIN11
* PTC7 - PIN12
* PTC8 - PIN28
* PTC9 - PIN27
* PTC10 - PIN29
* PTC11 - PIN30
*/
.port = IOPORT3,
.pads =
{
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
},
},
{
/*
* PORTD setup.
*
* PTD0 - PIN2
* PTD1 - PIN14
* PTD2 - PIN7
* PTD3 - PIN8
* PTD4 - PIN6
* PTD5 - PIN20
* PTD6 - PIN21
* PTD7 - PIN5
*/
.port = IOPORT4,
.pads =
{
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
},
},
{
/*
* PORTE setup.
*
* PTE0 - PIN31
* PTE1 - PIN26
*/
.port = IOPORT5,
.pads =
{
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
},
},
},
};
#endif
// NOTE: This value comes from kiibohd/controller and is the location of a value
// which needs to be checked before disabling the watchdog (which happens in
// k20x_clock_init)
#define WDOG_TMROUTL *(volatile uint16_t *)0x40052012
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
// This is a dirty hack and should only be used as a temporary fix until this
// is upstreamed.
while (WDOG_TMROUTL < 2)
; // Must wait for WDOG timer if already running, before jumping
k20x_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

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