migrate from electric vlsi to librelane/sky130 flowHEADmaster

this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).

this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.

1 files changed, 65 insertions, 0 deletions

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..8b7bf3a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,65 @@
+# ==============================================================================
+# CONFIGURATION
+# ==============================================================================
+PROJECT_NAME = lisp_coproc
+CONFIG_FILE  = config.json
+
+# Tool Paths
+LIBRELANE    = librelane
+VERILATOR    = verilator
+
+# PDK Paths (Standard Volare location)
+PDK_ROOT     ?= $(HOME)/.ciel/ciel/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/
+PDK          = sky130A
+LIB_VERILOG  = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+PRIM_VERILOG = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+
+# Simulation Flags
+VERILATOR_FLAGS = --binary -j 0 --timing --trace --top-module tb_$(PROJECT_NAME) \
+                  -Wno-fatal -Wno-style -Wno-lint
+
+# ==============================================================================
+# TARGETS
+# ==============================================================================
+.PHONY: all rtl harden gls clean
+
+# 1. Default: Run the full pipeline (RTL -> GDS -> Check)
+all: rtl harden gls
+
+# 2. RTL Verification: Runs your Golden SystemVerilog Testbench
+rtl:
+        @echo "\n=== [1/3] Running RTL Verification ==="
+        $(VERILATOR) $(VERILATOR_FLAGS) \
+                -DGL_SIM=0 \
+                rtl/tb_$(PROJECT_NAME).sv rtl/$(PROJECT_NAME).sv
+        ./obj_dir/Vtb_$(PROJECT_NAME)
+        @echo ">>> RTL Verification Passed <<<"
+
+# 3. Hardening: Runs LibreLane (Synthesis, Place & Route)
+# Note: Uses --run-tag to create a predictable folder name for the GLS step
+harden:
+        @echo "\n=== [2/3] Running LibreLane Hardening ==="
+        $(LIBRELANE) --flow Classic \
+                --run-tag automated_run \
+                --overwrite \
+                $(CONFIG_FILE)
+        @echo ">>> Hardening Complete <<<"
+
+# 4. Gate-Level Simulation (GLS): Verifies the final GDSII netlist
+# Finds the netlist generated by the 'harden' step
+GL_NETLIST = runs/automated_run/final/nl/$(PROJECT_NAME).nl.v
+
+gls:
+        @echo "\n=== [3/3] Running Gate-Level Simulation (GLS) ==="
+        $(VERILATOR) $(VERILATOR_FLAGS) \
+                -DGL_SIM=1 -DFUNCTIONAL -DUNIT_DELAY=\#1 \
+                -I$(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog \
+                rtl/tb_$(PROJECT_NAME).sv \
+                $(GL_NETLIST) \
+                $(LIB_VERILOG) $(PRIM_VERILOG)
+        ./obj_dir/Vtb_$(PROJECT_NAME)
+        @echo ">>> GLS Verification Passed <<<"
+
+# Clean up build artifacts
+clean:
+        rm -rf obj_dir runs/automated_run $(PROJECT_NAME).vcd