migrate from electric vlsi to librelane/sky130 flowHEADmaster

this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).

this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.

1 files changed, 6 insertions, 0 deletions

diff --git a/config.json b/config.json
new file mode 100644
index 0000000..0f2e115
--- /dev/null
+++ b/config.json
@@ -0,0 +1,6 @@
+{
+    "DESIGN_NAME": "lisp_coproc",
+    "VERILOG_FILES": ["dir::rtl/lisp_coproc.sv"],
+    "CLOCK_PERIOD": 100,
+    "CLOCK_PORT": "clk"
+}