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authorvin <git@vineetk.net>2025-12-10 16:35:42 -0500
committervin <git@vineetk.net>2025-12-10 16:39:36 -0500
commit06b6b116934cc8341676f52f5f6040a038020c32 (patch)
treef2db3531293b6de1a67a1e26a2aa1663f4d55082 /vlsi/toplevel.jelib
parent36f4ec74c5d1247362bed901dbaf0a36970b4cd0 (diff)
migrate from electric vlsi to librelane/sky130 flowHEADmaster
this is quite a major shift. moves the project from a manual, full-custom layout workflow to a more modern automated flow and a more modern process (130nm vs 350nm). also improved the testbench. migration also resolves previous manual routing-caused errors (like the CONS logic bug and difficulty in implementing TG logic). this nearly halved the transistor count from 15k to 8k and reduced area size by 300x.
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