1 files changed, 2 insertions, 2 deletions
diff --git a/vlsi/tb_chip_core.v b/vlsi/tb_chip_core.v
index 66fa212..b4a8925 100644
--- a/vlsi/tb_chip_core.v
+++ b/vlsi/tb_chip_core.v
@@ -115,13 +115,13 @@ module tb_chip_core;
    // ========================================================================
    initial begin
-        $dumpfile("chip_core_robust.vcd");
+        $dumpfile("chip_core.vcd");
        $dumpvars(0, tb_chip_core);
        
        // --- Initialize ---
        rst = 1; cs = 0; rw = 0; addr = 0; data_in = 0;
        #20 rst = 0; #20;
-        $display("\n=== STARTING ROBUST VERIFICATION ===\n");
+        $display("\n=== STARTING VERIFICATION ===\n");
        // --------------------------------------------------------
        // SCENARIO 1: ALU Boundary & Overflow

diff --git a/vlsi/tb_chip_core.v b/vlsi/tb_chip_core.v index 66fa212..b4a8925 100644 --- a/vlsi/tb_chip_core.v +++ b/vlsi/tb_chip_core.v
@@ -115,13 +115,13 @@ module tb_chip_core;
115	// ========================================================================	115	// ========================================================================
116		116
117	initial begin	117	initial begin
118	$dumpfile("chip_core_robust.vcd");	118	$dumpfile("chip_core.vcd");
119	$dumpvars(0, tb_chip_core);	119	$dumpvars(0, tb_chip_core);
120		120
121	// --- Initialize ---	121	// --- Initialize ---
122	rst = 1; cs = 0; rw = 0; addr = 0; data_in = 0;	122	rst = 1; cs = 0; rw = 0; addr = 0; data_in = 0;
123	#20 rst = 0; #20;	123	#20 rst = 0; #20;
124	$display("\n=== STARTING ROBUST VERIFICATION ===\n");	124	$display("\n=== STARTING VERIFICATION ===\n");
125		125
126	// --------------------------------------------------------	126	// --------------------------------------------------------
127	// SCENARIO 1: ALU Boundary & Overflow	127	// SCENARIO 1: ALU Boundary & Overflow