Makefile (2301B)
1 # ============================================================================== 2 # CONFIGURATION 3 # ============================================================================== 4 PROJECT_NAME = lisp_coproc 5 CONFIG_FILE = config.json 6 7 # Tool Paths 8 LIBRELANE = librelane 9 VERILATOR = verilator 10 11 # PDK Paths (Standard Volare location) 12 PDK_ROOT ?= $(HOME)/.ciel/ciel/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/ 13 PDK = sky130A 14 LIB_VERILOG = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v 15 PRIM_VERILOG = $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v 16 17 # Simulation Flags 18 VERILATOR_FLAGS = --binary -j 0 --timing --trace --top-module tb_$(PROJECT_NAME) \ 19 -Wno-fatal -Wno-style -Wno-lint 20 21 # ============================================================================== 22 # TARGETS 23 # ============================================================================== 24 .PHONY: all rtl harden gls clean 25 26 # 1. Default: Run the full pipeline (RTL -> GDS -> Check) 27 all: rtl harden gls 28 29 # 2. RTL Verification: Runs your Golden SystemVerilog Testbench 30 rtl: 31 @echo "\n=== [1/3] Running RTL Verification ===" 32 $(VERILATOR) $(VERILATOR_FLAGS) \ 33 -DGL_SIM=0 \ 34 rtl/tb_$(PROJECT_NAME).sv rtl/$(PROJECT_NAME).sv 35 ./obj_dir/Vtb_$(PROJECT_NAME) 36 @echo ">>> RTL Verification Passed <<<" 37 38 # 3. Hardening: Runs LibreLane (Synthesis, Place & Route) 39 # Note: Uses --run-tag to create a predictable folder name for the GLS step 40 harden: 41 @echo "\n=== [2/3] Running LibreLane Hardening ===" 42 $(LIBRELANE) --flow Classic \ 43 --run-tag automated_run \ 44 --overwrite \ 45 $(CONFIG_FILE) 46 @echo ">>> Hardening Complete <<<" 47 48 # 4. Gate-Level Simulation (GLS): Verifies the final GDSII netlist 49 # Finds the netlist generated by the 'harden' step 50 GL_NETLIST = runs/automated_run/final/nl/$(PROJECT_NAME).nl.v 51 52 gls: 53 @echo "\n=== [3/3] Running Gate-Level Simulation (GLS) ===" 54 $(VERILATOR) $(VERILATOR_FLAGS) \ 55 -DGL_SIM=1 -DFUNCTIONAL -DUNIT_DELAY=\#1 \ 56 -I$(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog \ 57 rtl/tb_$(PROJECT_NAME).sv \ 58 $(GL_NETLIST) \ 59 $(LIB_VERILOG) $(PRIM_VERILOG) 60 ./obj_dir/Vtb_$(PROJECT_NAME) 61 @echo ">>> GLS Verification Passed <<<" 62 63 # Clean up build artifacts 64 clean: 65 rm -rf obj_dir runs/automated_run $(PROJECT_NAME).vcd