| 2025-12-10 21:35 | migrate from electric vlsi to librelane/sky130 flow | vin | 6 | +631 | -510 |
| 2025-12-09 03:19 | final changes from electric before moving to librelane | vin | 8 | +10997 | -309 |
| 2025-12-01 22:13 | fix mux16 layout input ordering | vin | 1 | +77 | -76 |
| 2025-12-01 21:13 | some more changes | vin | 1 | +1230 | -113 |
| 2025-11-30 07:38 | add more gates and make some changes to layouts for easier tiling | vin | 3 | +2158 | -410 |
| 2025-11-29 07:08 | add 6-bit rca and 8-bit equivalent | vin | 2 | +829 | -84 |
| 2025-11-28 12:05 | finish making primitive cells (passes DRC+ERC+LVS) | vin | 1 | +1189 | -0 |
| 2025-11-20 17:01 | add more comprehensive test bench | vin | 1 | +254 | -94 |
| 2025-11-20 16:27 | fix lint errors from icarus-verilog and verilator | vin | 1 | +10 | -5 |
| 2025-11-20 16:16 | fix rtl, now tests all pass | vin | 3 | +240 | -318 |
| 2025-11-20 16:01 | initial golden rtl | vin | 3 | +443 | -0 |
