chip_core.v (29962B)
1 /* Verilog for cell 'chip_core{sch}' from library 'toplevel' */ 2 /* Created on Thu Dec 04, 2025 14:22:13 */ 3 /* Last revised on Thu Dec 04, 2025 21:10:21 */ 4 /* Written on Thu Dec 04, 2025 21:10:31 by Electric VLSI Design System, version 9.08 */ 5 6 module stdcells__inv(x, y); 7 input x; 8 output y; 9 10 assign y = ~x; 11 endmodule /* stdcells__inv */ 12 13 module stdcells__nand2(x, y, z); 14 input x; 15 input y; 16 output z; 17 18 assign z = ~(x & y); 19 endmodule /* stdcells__nand2 */ 20 21 module stdcells__mux2(i, s, z); 22 input [1:0] i; 23 input s; 24 output z; 25 26 supply1 vdd; 27 supply0 gnd; 28 wire net_28, net_32, net_36; 29 30 stdcells__inv inv2_4(.x(s), .y(net_36)); 31 stdcells__nand2 nand2_0(.x(i[1]), .y(s), .z(net_28)); 32 stdcells__nand2 nand2_1(.x(i[0]), .y(net_36), .z(net_32)); 33 stdcells__nand2 nand2_2(.x(net_28), .y(net_32), .z(z)); 34 endmodule /* stdcells__mux2 */ 35 36 module stdcells__tielow(y); 37 output y; 38 39 assign y = 0; 40 endmodule /* stdcells__tielow */ 41 42 module stdcells__dff(clk, d, rst, q); 43 input clk; 44 input d; 45 input rst; 46 output reg q; // 'reg' is needed for behavioral assignment 47 48 always @(posedge clk or posedge rst) begin 49 if (rst) begin 50 q <= 1'b0; // Async Reset (Active High) 51 end else begin 52 q <= d; // Data Capture 53 end 54 end 55 endmodule 56 57 module memory__dffe(clk, d, en, rst, q); 58 input clk; 59 input d; 60 input en; 61 input rst; 62 output q; 63 64 supply1 vdd; 65 supply0 gnd; 66 wire net_5; 67 68 stdcells__dff dff_0(.clk(clk), .d(net_5), .rst(rst), .q(q)); 69 stdcells__mux2 mux2_0(.i({d, q}), .s(en), .z(net_5)); 70 endmodule /* memory__dffe */ 71 72 module stdcells__xor2(x, y, z); 73 input x; 74 input y; 75 output z; 76 77 supply1 vdd; 78 supply0 gnd; 79 wire net_17, net_24, net_25; 80 81 stdcells__nand2 nand2_0(.x(x), .y(y), .z(net_17)); 82 stdcells__nand2 nand2_1(.x(x), .y(net_17), .z(net_24)); 83 stdcells__nand2 nand2_2(.x(net_24), .y(net_25), .z(z)); 84 stdcells__nand2 nand2_3(.x(y), .y(net_17), .z(net_25)); 85 endmodule /* stdcells__xor2 */ 86 87 module memory__bumpallocator(clk, inc_en, rst, ptr); 88 input clk; 89 input inc_en; 90 input rst; 91 output [3:0] ptr; 92 93 supply1 vdd; 94 supply0 gnd; 95 wire net_27, net_34, net_57, net_59, net_68; 96 97 memory__dffe dffe_0(.clk(clk), .d(ptr[0]), .en(inc_en), .rst(rst), 98 .q(ptr[0])); 99 memory__dffe dffe_1(.clk(clk), .d(net_27), .en(inc_en), .rst(rst), 100 .q(ptr[1])); 101 memory__dffe dffe_2(.clk(clk), .d(net_34), .en(inc_en), .rst(rst), 102 .q(ptr[2])); 103 memory__dffe dffe_3(.clk(clk), .d(net_68), .en(inc_en), .rst(rst), 104 .q(ptr[3])); 105 stdcells__inv inv_2(.x(ptr[1]), .y(net_27)); 106 stdcells__inv inv_3(.x(net_57), .y(net_59)); 107 stdcells__nand2 nand2_1(.x(ptr[1]), .y(ptr[2]), .z(net_57)); 108 stdcells__xor2 xor2_2(.x(ptr[2]), .y(ptr[1]), .z(net_34)); 109 stdcells__xor2 xor2_3(.x(ptr[3]), .y(net_59), .z(net_68)); 110 endmodule /* memory__bumpallocator */ 111 112 module stdcells__nor2(x, y, z); 113 input x; 114 input y; 115 output z; 116 117 assign z = ~(x | y); 118 endmodule /* stdcells__nor2 */ 119 120 module datapath__eq_8bit(a, b, eq); 121 input [7:0] a; 122 input [7:0] b; 123 output eq; 124 125 supply1 vdd; 126 supply0 gnd; 127 wire net_4, net_5, net_6, net_7, net_8, net_9, net_10, net_12, net_14, net_16; 128 wire net_18, net_21, net_24, net_26; 129 130 stdcells__nand2 nand2_0(.x(net_4), .y(net_5), .z(net_24)); 131 stdcells__nand2 nand2_1(.x(net_6), .y(net_7), .z(net_26)); 132 stdcells__nor2 nor2_0(.x(net_21), .y(net_16), .z(net_4)); 133 stdcells__nor2 nor2_1(.x(net_14), .y(net_8), .z(net_5)); 134 stdcells__nor2 nor2_2(.x(net_9), .y(net_10), .z(net_6)); 135 stdcells__nor2 nor2_3(.x(net_12), .y(net_18), .z(net_7)); 136 stdcells__nor2 nor2_4(.x(net_24), .y(net_26), .z(eq)); 137 stdcells__xor2 xor2_1(.x(a[0]), .y(b[0]), .z(net_21)); 138 stdcells__xor2 xor2_2(.x(a[1]), .y(b[1]), .z(net_16)); 139 stdcells__xor2 xor2_3(.x(a[2]), .y(b[2]), .z(net_14)); 140 stdcells__xor2 xor2_4(.x(a[3]), .y(b[3]), .z(net_8)); 141 stdcells__xor2 xor2_5(.x(a[4]), .y(b[4]), .z(net_9)); 142 stdcells__xor2 xor2_6(.x(a[5]), .y(b[5]), .z(net_10)); 143 stdcells__xor2 xor2_7(.x(a[6]), .y(b[6]), .z(net_12)); 144 stdcells__xor2 xor2_8(.x(a[7]), .y(b[7]), .z(net_18)); 145 endmodule /* datapath__eq_8bit */ 146 147 module stdcells__nand3(w, x, y, z); 148 input w; 149 input x; 150 input y; 151 output z; 152 153 assign z = ~(w & x & y); 154 endmodule /* stdcells__nand3 */ 155 156 module control__fsm(a, clk, cs, op, rst, rw, alu_en, busy, heap_wen, 157 q_exec_cdr, reg_wen); 158 input [2:0] a; 159 input clk; 160 input cs; 161 input [2:0] op; 162 input rst; 163 input rw; 164 output alu_en; 165 output busy; 166 output heap_wen; 167 output q_exec_cdr; 168 output reg_wen; 169 170 supply1 vdd; 171 supply0 gnd; 172 wire _all_zeros, _stay, cons_first_half, net_24, net_26, net_31, net_33; 173 wire net_35, net_37, net_38, net_40, net_42, net_53, net_59, net_70, net_79; 174 wire net_108, net_134, net_142, net_144, net_161, net_172, net_228, net_229; 175 wire q_decode, q_idle; 176 177 stdcells__dff dff_1(.clk(clk), .d(net_108), .rst(rst), .q(q_idle)); 178 stdcells__dff dff_2(.clk(clk), .d(net_161), .rst(rst), .q(reg_wen)); 179 stdcells__dff dff_3(.clk(clk), .d(cons_first_half), .rst(rst), 180 .q(q_exec_cdr)); 181 stdcells__dff dff_4(.clk(clk), .d(net_59), .rst(rst), .q(q_decode)); 182 stdcells__dff dff_5(.clk(clk), .d(q_decode), .rst(rst), .q(alu_en)); 183 stdcells__inv inv_0(.x(rw), .y(net_31)); 184 stdcells__inv inv_1(.x(a[0]), .y(net_35)); 185 stdcells__inv inv_2(.x(a[1]), .y(net_37)); 186 stdcells__inv inv_3(.x(a[2]), .y(net_33)); 187 stdcells__inv inv_5(.x(net_53), .y(net_59)); 188 stdcells__inv inv_6(.x(net_38), .y(net_70)); 189 stdcells__inv inv_7(.x(reg_wen), .y(net_79)); 190 stdcells__inv inv_8(.x(q_idle), .y(busy)); 191 stdcells__inv inv_11(.x(alu_en), .y(net_134)); 192 stdcells__inv inv_12(.x(q_exec_cdr), .y(net_144)); 193 stdcells__inv inv_13(.x(net_172), .y(heap_wen)); 194 stdcells__nand2 nand2_0(.x(net_35), .y(net_37), .z(net_26)); 195 stdcells__nand2 nand2_1(.x(net_42), .y(net_40), .z(_all_zeros)); 196 stdcells__nand2 nand2_2(.x(net_38), .y(q_idle), .z(net_53)); 197 stdcells__nand2 nand2_3(.x(net_70), .y(q_idle), .z(_stay)); 198 stdcells__nand2 nand2_4(.x(net_228), .y(alu_en), .z(net_142)); 199 stdcells__nand2 nand2_5(.x(net_142), .y(net_144), .z(net_161)); 200 stdcells__nand2 nand2_6(.x(op[0]), .y(net_229), .z(net_228)); 201 stdcells__nand3 nand3_0(.w(cs), .x(net_31), .y(net_33), .z(net_24)); 202 stdcells__nand3 nand3_1(.w(_stay), .x(net_79), .y(_all_zeros), .z(net_108)); 203 stdcells__nor2 nor2_0(.x(net_24), .y(net_26), .z(net_38)); 204 stdcells__nor2 nor2_1(.x(reg_wen), .y(alu_en), .z(net_42)); 205 stdcells__nor2 nor2_2(.x(q_decode), .y(q_idle), .z(net_40)); 206 stdcells__nor2 nor2_3(.x(net_134), .y(net_228), .z(cons_first_half)); 207 stdcells__nor2 nor2_4(.x(cons_first_half), .y(q_exec_cdr), .z(net_172)); 208 stdcells__nor2 nor2_5(.x(op[1]), .y(op[2]), .z(net_229)); 209 endmodule /* control__fsm */ 210 211 module stdcells__dec2(a0, a1, en, _q0, _q1, _q2, _q3); 212 input a0; 213 input a1; 214 input en; 215 output _q0; 216 output _q1; 217 output _q2; 218 output _q3; 219 220 supply1 vdd; 221 supply0 gnd; 222 wire net_20, net_24; 223 224 stdcells__inv inv_0(.x(a0), .y(net_20)); 225 stdcells__inv inv_1(.x(a1), .y(net_24)); 226 stdcells__nand3 nand3_0(.w(net_20), .x(net_24), .y(en), .z(_q0)); 227 stdcells__nand3 nand3_1(.w(net_20), .x(a1), .y(en), .z(_q1)); 228 stdcells__nand3 nand3_2(.w(a0), .x(net_24), .y(en), .z(_q2)); 229 stdcells__nand3 nand3_3(.w(a0), .x(a1), .y(en), .z(_q3)); 230 endmodule /* stdcells__dec2 */ 231 232 module datapath__mux2_8bit(i0, i1, s, z); 233 input [7:0] i0; 234 input [7:0] i1; 235 input s; 236 output [7:0] z; 237 238 supply1 vdd; 239 supply0 gnd; 240 stdcells__mux2 mux2_0(.i({i1[0], i0[0]}), .s(s), .z(z[0])); 241 stdcells__mux2 mux2_1(.i({i1[1], i0[1]}), .s(s), .z(z[1])); 242 stdcells__mux2 mux2_2(.i({i1[2], i0[2]}), .s(s), .z(z[2])); 243 stdcells__mux2 mux2_3(.i({i1[3], i0[3]}), .s(s), .z(z[3])); 244 stdcells__mux2 mux2_4(.i({i1[4], i0[4]}), .s(s), .z(z[4])); 245 stdcells__mux2 mux2_5(.i({i1[5], i0[5]}), .s(s), .z(z[5])); 246 stdcells__mux2 mux2_6(.i({i1[6], i0[6]}), .s(s), .z(z[6])); 247 stdcells__mux2 mux2_7(.i({i1[7], i0[7]}), .s(s), .z(z[7])); 248 endmodule /* datapath__mux2_8bit */ 249 250 module datapath__mux4(i, s, z); 251 input [3:0] i; 252 input [1:0] s; 253 output z; 254 255 supply1 vdd; 256 supply0 gnd; 257 wire net_1, net_4; 258 259 stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_1)); 260 stdcells__mux2 mux2_1(.i(i[3:2]), .s(s[0]), .z(net_4)); 261 stdcells__mux2 mux2_2(.i({net_4, net_1}), .s(s[1]), .z(z)); 262 endmodule /* datapath__mux4 */ 263 264 module datapath__mux4_8bit(i0, i1, i2, i3, s, z); 265 input [7:0] i0; 266 input [7:0] i1; 267 input [7:0] i2; 268 input [7:0] i3; 269 input [1:0] s; 270 output [7:0] z; 271 272 supply1 vdd; 273 supply0 gnd; 274 datapath__mux4 mux4_0(.i({i3[0], i2[0], i1[0], i0[0]}), .s(s[1:0]), 275 .z(z[0])); 276 datapath__mux4 mux4_1(.i({i3[1], i2[1], i1[1], i0[1]}), .s(s[1:0]), 277 .z(z[1])); 278 datapath__mux4 mux4_2(.i({i3[2], i2[2], i1[2], i0[2]}), .s(s[1:0]), 279 .z(z[2])); 280 datapath__mux4 mux4_3(.i({i3[3], i2[3], i1[3], i0[3]}), .s(s[1:0]), 281 .z(z[3])); 282 datapath__mux4 mux4_4(.i({i3[4], i2[4], i1[4], i0[4]}), .s(s[1:0]), 283 .z(z[4])); 284 datapath__mux4 mux4_5(.i({i3[5], i2[5], i1[5], i0[5]}), .s(s[1:0]), 285 .z(z[5])); 286 datapath__mux4 mux4_6(.i({i3[6], i2[6], i1[6], i0[6]}), .s(s[1:0]), 287 .z(z[6])); 288 datapath__mux4 mux4_7(.i({i3[7], i2[7], i1[7], i0[7]}), .s(s[1:0]), 289 .z(z[7])); 290 endmodule /* datapath__mux4_8bit */ 291 292 module memory__reg8(clk, d, en, rst, q); 293 input clk; 294 input [7:0] d; 295 input en; 296 input rst; 297 output [7:0] q; 298 299 supply1 vdd; 300 supply0 gnd; 301 memory__dffe dffe_2(.clk(clk), .d(d[7]), .en(en), .rst(rst), .q(q[7])); 302 memory__dffe dffe_8(.clk(clk), .d(d[6]), .en(en), .rst(rst), .q(q[6])); 303 memory__dffe dffe_9(.clk(clk), .d(d[5]), .en(en), .rst(rst), .q(q[5])); 304 memory__dffe dffe_10(.clk(clk), .d(d[4]), .en(en), .rst(rst), .q(q[4])); 305 memory__dffe dffe_11(.clk(clk), .d(d[3]), .en(en), .rst(rst), .q(q[3])); 306 memory__dffe dffe_12(.clk(clk), .d(d[2]), .en(en), .rst(rst), .q(q[2])); 307 memory__dffe dffe_13(.clk(clk), .d(d[1]), .en(en), .rst(rst), .q(q[1])); 308 memory__dffe dffe_14(.clk(clk), .d(d[0]), .en(en), .rst(rst), .q(q[0])); 309 endmodule /* memory__reg8 */ 310 311 module stdcells__tiehigh(y); 312 output y; 313 314 assign y = 1; 315 endmodule /* stdcells__tiehigh */ 316 317 module memory__ioreg5(a, clk, data_in, global_en, reg_wen, result_in, rst, 318 status_busy, status_carry, status_err_heap, status_err_type, status_zero, 319 data_out, q_arg1, q_arg2, q_opcode); 320 input [2:0] a; 321 input clk; 322 input [7:0] data_in; 323 input global_en; 324 input reg_wen; 325 input [7:0] result_in; 326 input rst; 327 input status_busy; 328 input status_carry; 329 input status_err_heap; 330 input status_err_type; 331 input status_zero; 332 output [7:0] data_out; 333 output [7:0] q_arg1; 334 output [7:0] q_arg2; 335 output [7:0] q_opcode; 336 337 supply1 vdd; 338 supply0 gnd; 339 wire net_35, net_36, net_37, net_44, net_45, net_52, net_73, net_75, net_76; 340 wire net_145, net_147, net_148, net_314, net_345, net_346, net_517, net_520; 341 wire net_523, net_526, net_529, net_532, net_535, net_617, net_619, net_621; 342 wire net_623, net_625, net_627, net_629, net_631, net_778, net_780, net_783; 343 wire net_786, net_789, net_792, net_795, net_869, net_1080, net_1328; 344 wire net_1330, net_1334, net_1338, net_1342, net_1346, net_1350, net_1354; 345 346 stdcells__dec2 dec2_0(.a0(a[0]), .a1(a[1]), .en(net_76), ._q0(net_52), 347 ._q1(net_314), ._q2(net_45), ._q3(net_44)); 348 stdcells__inv inv_2(.x(net_45), .y(net_37)); 349 stdcells__inv inv_3(.x(net_314), .y(net_36)); 350 stdcells__inv inv_4(.x(net_52), .y(net_35)); 351 stdcells__inv inv_5(.x(a[2]), .y(net_75)); 352 stdcells__inv inv_6(.x(net_73), .y(net_76)); 353 stdcells__inv inv_8(.x(net_147), .y(net_148)); 354 stdcells__inv inv_9(.x(net_44), .y(net_145)); 355 datapath__mux2_8bit mux2_8bi_0(.i0({net_1080, net_795, net_792, net_789, 356 net_786, net_783, net_780, net_778}), .i1({net_617, net_619, net_621, 357 net_623, net_625, net_627, net_629, net_631}), .s(a[2]), 358 .z(data_out[7:0])); 359 datapath__mux2_8bit mux2_8bi_1(.i0(data_in[7:0]), .i1(result_in[7:0]), 360 .s(reg_wen), .z({net_1328, net_1330, net_1334, net_1338, net_1342, 361 net_1346, net_1350, net_1354})); 362 datapath__mux4_8bit mux4_8bi_1(.i0(q_opcode[7:0]), .i1(q_arg1[7:0]), 363 .i2(q_arg2[7:0]), .i3({net_535, net_532, net_529, net_526, net_523, 364 net_520, net_517, net_869}), .s(a[1:0]), .z({net_1080, net_795, net_792, 365 net_789, net_786, net_783, net_780, net_778})); 366 stdcells__nand2 nand2_0(.x(net_75), .y(global_en), .z(net_73)); 367 stdcells__nor2 nor2_0(.x(reg_wen), .y(net_145), .z(net_147)); 368 memory__reg8 reg8_0(.clk(clk), .d({net_346, net_346, net_346, status_zero, 369 status_carry, status_err_type, status_err_heap, status_busy}), 370 .en(net_345), .rst(rst), .q({net_617, net_619, net_621, net_623, net_625, 371 net_627, net_629, net_631})); 372 memory__reg8 reg8_1(.clk(clk), .d({net_1328, net_1330, net_1334, net_1338, 373 net_1342, net_1346, net_1350, net_1354}), .en(net_148), .rst(rst), 374 .q({net_535, net_532, net_529, net_526, net_523, net_520, net_517, 375 net_869})); 376 memory__reg8 reg8_2(.clk(clk), .d(data_in[7:0]), .en(net_37), .rst(rst), 377 .q(q_arg2[7:0])); 378 memory__reg8 reg8_3(.clk(clk), .d(data_in[7:0]), .en(net_36), .rst(rst), 379 .q(q_arg1[7:0])); 380 memory__reg8 reg8_4(.clk(clk), .d(data_in[7:0]), .en(net_35), .rst(rst), 381 .q(q_opcode[7:0])); 382 stdcells__tiehigh tiehigh_0(.y(net_345)); 383 stdcells__tielow tielow_0(.y(net_346)); 384 endmodule /* memory__ioreg5 */ 385 386 module datapath__mux3(i, s, z); 387 input [2:0] i; 388 input [1:0] s; 389 output z; 390 391 supply1 vdd; 392 supply0 gnd; 393 wire net_5; 394 395 stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_5)); 396 stdcells__mux2 mux2_1(.i({i[2], net_5}), .s(s[1]), .z(z)); 397 endmodule /* datapath__mux3 */ 398 399 module datapath__mux3_4bit(i0, i1, i2, s, z); 400 input [3:0] i0; 401 input [3:0] i1; 402 input [3:0] i2; 403 input [1:0] s; 404 output [3:0] z; 405 406 supply1 vdd; 407 supply0 gnd; 408 datapath__mux3 mux3_0(.i({i2[0], i1[0], i0[0]}), .s(s[1:0]), .z(z[0])); 409 datapath__mux3 mux3_1(.i({i2[1], i1[1], i0[1]}), .s(s[1:0]), .z(z[1])); 410 datapath__mux3 mux3_2(.i({i2[2], i1[2], i0[2]}), .s(s[1:0]), .z(z[2])); 411 datapath__mux3 mux3_3(.i({i2[3], i1[3], i0[3]}), .s(s[1:0]), .z(z[3])); 412 endmodule /* datapath__mux3_4bit */ 413 414 module stdcells__fa(a, b, cin, cout, s); 415 input a; 416 input b; 417 input cin; 418 output cout; 419 output s; 420 421 supply1 vdd; 422 supply0 gnd; 423 wire net_4; 424 425 stdcells__mux2 mux2_0(.i({cin, a}), .s(net_4), .z(cout)); 426 stdcells__xor2 xor2_0(.x(a), .y(b), .z(net_4)); 427 stdcells__xor2 xor2_1(.x(net_4), .y(cin), .z(s)); 428 endmodule /* stdcells__fa */ 429 430 module datapath__rca_6bit(a, b, cin, cout, s); 431 input [5:0] a; 432 input [5:0] b; 433 input cin; 434 output cout; 435 output [5:0] s; 436 437 supply1 vdd; 438 supply0 gnd; 439 wire net_2, net_3, net_4, net_5, net_10; 440 441 stdcells__fa fa_0_(.a(a[0]), .b(b[0]), .cin(cin), .cout(net_5), .s(s[0])); 442 stdcells__fa fa_1_(.a(a[1]), .b(b[1]), .cin(net_5), .cout(net_4), .s(s[1])); 443 stdcells__fa fa_2_(.a(a[2]), .b(b[2]), .cin(net_4), .cout(net_3), .s(s[2])); 444 stdcells__fa fa_3_(.a(a[3]), .b(b[3]), .cin(net_3), .cout(net_10), 445 .s(s[3])); 446 stdcells__fa fa_4_(.a(a[4]), .b(b[4]), .cin(net_10), .cout(net_2), 447 .s(s[4])); 448 stdcells__fa fa_5_(.a(a[5]), .b(b[5]), .cin(net_2), .cout(cout), .s(s[5])); 449 endmodule /* datapath__rca_6bit */ 450 451 module memory__dec4(a, en, q); 452 input [3:0] a; 453 input en; 454 output [15:0] q; 455 456 supply1 vdd; 457 supply0 gnd; 458 wire net_5, net_17, net_20, net_23, net_62, net_76, net_88, net_89; 459 460 stdcells__dec2 dec2_0(.a0(a[3]), .a1(a[2]), .en(en), ._q0(net_5), 461 ._q1(net_17), ._q2(net_20), ._q3(net_23)); 462 stdcells__dec2 dec2_1(.a0(a[1]), .a1(a[0]), .en(en), ._q0(net_62), 463 ._q1(net_76), ._q2(net_88), ._q3(net_89)); 464 stdcells__nor2 nor2_0(.x(net_5), .y(net_62), .z(q[0])); 465 stdcells__nor2 nor2_1(.x(net_5), .y(net_76), .z(q[1])); 466 stdcells__nor2 nor2_2(.x(net_5), .y(net_88), .z(q[2])); 467 stdcells__nor2 nor2_3(.x(net_5), .y(net_89), .z(q[3])); 468 stdcells__nor2 nor2_4(.x(net_17), .y(net_62), .z(q[4])); 469 stdcells__nor2 nor2_5(.x(net_17), .y(net_76), .z(q[5])); 470 stdcells__nor2 nor2_6(.x(net_17), .y(net_88), .z(q[6])); 471 stdcells__nor2 nor2_7(.x(net_17), .y(net_89), .z(q[7])); 472 stdcells__nor2 nor2_8(.x(net_20), .y(net_62), .z(q[8])); 473 stdcells__nor2 nor2_9(.x(net_20), .y(net_76), .z(q[9])); 474 stdcells__nor2 nor2_10(.x(net_20), .y(net_88), .z(q[10])); 475 stdcells__nor2 nor2_11(.x(net_20), .y(net_89), .z(q[11])); 476 stdcells__nor2 nor2_12(.x(net_23), .y(net_62), .z(q[12])); 477 stdcells__nor2 nor2_13(.x(net_23), .y(net_76), .z(q[13])); 478 stdcells__nor2 nor2_14(.x(net_23), .y(net_88), .z(q[14])); 479 stdcells__nor2 nor2_15(.x(net_23), .y(net_89), .z(q[15])); 480 endmodule /* memory__dec4 */ 481 482 module memory__mux16(i, s, z); 483 input [15:0] i; 484 input [3:0] s; 485 output z; 486 487 supply1 vdd; 488 supply0 gnd; 489 wire net_65, net_67, net_70, net_72, net_75, net_77, net_80, net_82, net_85; 490 wire net_87, net_88, net_90, net_95, net_97; 491 492 stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_65)); 493 stdcells__mux2 mux2_1(.i({i[2], i[3]}), .s(s[0]), .z(net_67)); 494 stdcells__mux2 mux2_2(.i(i[5:4]), .s(s[0]), .z(net_72)); 495 stdcells__mux2 mux2_3(.i({i[6], i[7]}), .s(s[0]), .z(net_70)); 496 stdcells__mux2 mux2_4(.i(i[9:8]), .s(s[0]), .z(net_75)); 497 stdcells__mux2 mux2_5(.i({i[10], i[11]}), .s(s[0]), .z(net_77)); 498 stdcells__mux2 mux2_6(.i(i[13:12]), .s(s[0]), .z(net_80)); 499 stdcells__mux2 mux2_7(.i({i[14], i[15]}), .s(s[0]), .z(net_82)); 500 stdcells__mux2 mux2_8(.i({net_67, net_65}), .s(s[1]), .z(net_85)); 501 stdcells__mux2 mux2_9(.i({net_70, net_72}), .s(s[1]), .z(net_87)); 502 stdcells__mux2 mux2_10(.i({net_77, net_75}), .s(s[1]), .z(net_88)); 503 stdcells__mux2 mux2_11(.i({net_82, net_80}), .s(s[1]), .z(net_90)); 504 stdcells__mux2 mux2_12(.i({net_87, net_85}), .s(s[2]), .z(net_97)); 505 stdcells__mux2 mux2_13(.i({net_90, net_88}), .s(s[2]), .z(net_95)); 506 stdcells__mux2 mux2_14(.i({net_95, net_97}), .s(s[3]), .z(z)); 507 endmodule /* memory__mux16 */ 508 509 module memory__regfile16(clk, r_addr, rst, w_addr, w_data, w_en, r_data); 510 input clk; 511 input [3:0] r_addr; 512 input rst; 513 input [3:0] w_addr; 514 input [7:0] w_data; 515 input w_en; 516 output [7:0] r_data; 517 518 supply1 vdd; 519 supply0 gnd; 520 wire net_0, net_99, net_102, net_103, net_104, net_105, net_106, net_107; 521 wire net_108, net_109, net_110, net_111, net_112, net_113, net_114, net_115; 522 wire net_413, net_414, net_415, net_416, net_417, net_418, net_419, net_420; 523 wire net_424, net_425, net_426, net_427, net_428, net_429, net_430, net_431; 524 wire net_432, net_433, net_434, net_435, net_436, net_437, net_438, net_439; 525 wire net_440, net_441, net_442, net_443, net_444, net_445, net_446, net_447; 526 wire net_448, net_449, net_450, net_451, net_452, net_453, net_454, net_455; 527 wire net_456, net_457, net_458, net_459, net_460, net_461, net_462, net_463; 528 wire net_464, net_465, net_466, net_467, net_468, net_469, net_470, net_471; 529 wire net_472, net_473, net_474, net_475, net_476, net_477, net_478, net_479; 530 wire net_480, net_481, net_482, net_483, net_484, net_485, net_486, net_487; 531 wire net_488, net_489, net_490, net_491, net_492, net_493, net_494, net_495; 532 wire net_496, net_497, net_498, net_499, net_500, net_501, net_502, net_503; 533 wire net_504, net_505, net_506, net_507, net_508, net_509, net_510, net_511; 534 wire net_512, net_513, net_514, net_515, net_516, net_517, net_518, net_519; 535 wire net_520, net_521, net_522, net_523, net_524, net_525, net_526, net_527; 536 wire net_528, net_529, net_530, net_531, net_532, net_533, net_534, net_535; 537 wire net_536, net_537, net_538, net_539, net_540, net_541, net_542, net_543; 538 539 memory__dec4 dec4_0(.a(w_addr[3:0]), .en(w_en), .q({net_115, net_114, 540 net_113, net_112, net_111, net_110, net_109, net_108, net_107, net_106, 541 net_105, net_104, net_103, net_102, net_99, net_0})); 542 memory__mux16 mux16_0(.i({net_413, net_431, net_439, net_447, net_455, 543 net_463, net_471, net_479, net_487, net_495, net_503, net_511, net_519, 544 net_527, net_535, net_543}), .s(r_addr[3:0]), .z(r_data[7])); 545 memory__mux16 mux16_1(.i({net_414, net_430, net_438, net_446, net_454, 546 net_462, net_470, net_478, net_486, net_494, net_502, net_510, net_518, 547 net_526, net_534, net_542}), .s(r_addr[3:0]), .z(r_data[6])); 548 memory__mux16 mux16_2(.i({net_415, net_429, net_437, net_445, net_453, 549 net_461, net_469, net_477, net_485, net_493, net_501, net_509, net_517, 550 net_525, net_533, net_541}), .s(r_addr[3:0]), .z(r_data[5])); 551 memory__mux16 mux16_3(.i({net_416, net_428, net_436, net_444, net_452, 552 net_460, net_468, net_476, net_484, net_492, net_500, net_508, net_516, 553 net_524, net_532, net_540}), .s(r_addr[3:0]), .z(r_data[4])); 554 memory__mux16 mux16_4(.i({net_417, net_427, net_435, net_443, net_451, 555 net_459, net_467, net_475, net_483, net_491, net_499, net_507, net_515, 556 net_523, net_531, net_539}), .s(r_addr[3:0]), .z(r_data[3])); 557 memory__mux16 mux16_5(.i({net_418, net_426, net_434, net_442, net_450, 558 net_458, net_466, net_474, net_482, net_490, net_498, net_506, net_514, 559 net_522, net_530, net_538}), .s(r_addr[3:0]), .z(r_data[2])); 560 memory__mux16 mux16_6(.i({net_419, net_425, net_433, net_441, net_449, 561 net_457, net_465, net_473, net_481, net_489, net_497, net_505, net_513, 562 net_521, net_529, net_537}), .s(r_addr[3:0]), .z(r_data[1])); 563 memory__mux16 mux16_7(.i({net_420, net_424, net_432, net_440, net_448, 564 net_456, net_464, net_472, net_480, net_488, net_496, net_504, net_512, 565 net_520, net_528, net_536}), .s(r_addr[3:0]), .z(r_data[0])); 566 memory__reg8 reg8_0(.clk(clk), .d(w_data[7:0]), .en(net_0), .rst(rst), 567 .q({net_543, net_542, net_541, net_540, net_539, net_538, net_537, 568 net_536})); 569 memory__reg8 reg8_1(.clk(clk), .d(w_data[7:0]), .en(net_99), .rst(rst), 570 .q({net_535, net_534, net_533, net_532, net_531, net_530, net_529, 571 net_528})); 572 memory__reg8 reg8_2(.clk(clk), .d(w_data[7:0]), .en(net_102), .rst(rst), 573 .q({net_527, net_526, net_525, net_524, net_523, net_522, net_521, 574 net_520})); 575 memory__reg8 reg8_3(.clk(clk), .d(w_data[7:0]), .en(net_103), .rst(rst), 576 .q({net_519, net_518, net_517, net_516, net_515, net_514, net_513, 577 net_512})); 578 memory__reg8 reg8_4(.clk(clk), .d(w_data[7:0]), .en(net_104), .rst(rst), 579 .q({net_511, net_510, net_509, net_508, net_507, net_506, net_505, 580 net_504})); 581 memory__reg8 reg8_5(.clk(clk), .d(w_data[7:0]), .en(net_105), .rst(rst), 582 .q({net_503, net_502, net_501, net_500, net_499, net_498, net_497, 583 net_496})); 584 memory__reg8 reg8_6(.clk(clk), .d(w_data[7:0]), .en(net_106), .rst(rst), 585 .q({net_495, net_494, net_493, net_492, net_491, net_490, net_489, 586 net_488})); 587 memory__reg8 reg8_7(.clk(clk), .d(w_data[7:0]), .en(net_107), .rst(rst), 588 .q({net_487, net_486, net_485, net_484, net_483, net_482, net_481, 589 net_480})); 590 memory__reg8 reg8_8(.clk(clk), .d(w_data[7:0]), .en(net_108), .rst(rst), 591 .q({net_479, net_478, net_477, net_476, net_475, net_474, net_473, 592 net_472})); 593 memory__reg8 reg8_9(.clk(clk), .d(w_data[7:0]), .en(net_109), .rst(rst), 594 .q({net_471, net_470, net_469, net_468, net_467, net_466, net_465, 595 net_464})); 596 memory__reg8 reg8_10(.clk(clk), .d(w_data[7:0]), .en(net_110), .rst(rst), 597 .q({net_463, net_462, net_461, net_460, net_459, net_458, net_457, 598 net_456})); 599 memory__reg8 reg8_11(.clk(clk), .d(w_data[7:0]), .en(net_111), .rst(rst), 600 .q({net_455, net_454, net_453, net_452, net_451, net_450, net_449, 601 net_448})); 602 memory__reg8 reg8_12(.clk(clk), .d(w_data[7:0]), .en(net_112), .rst(rst), 603 .q({net_447, net_446, net_445, net_444, net_443, net_442, net_441, 604 net_440})); 605 memory__reg8 reg8_13(.clk(clk), .d(w_data[7:0]), .en(net_113), .rst(rst), 606 .q({net_439, net_438, net_437, net_436, net_435, net_434, net_433, 607 net_432})); 608 memory__reg8 reg8_14(.clk(clk), .d(w_data[7:0]), .en(net_114), .rst(rst), 609 .q({net_431, net_430, net_429, net_428, net_427, net_426, net_425, 610 net_424})); 611 memory__reg8 reg8_15(.clk(clk), .d(w_data[7:0]), .en(net_115), .rst(rst), 612 .q({net_413, net_414, net_415, net_416, net_417, net_418, net_419, 613 net_420})); 614 endmodule /* memory__regfile16 */ 615 616 module chip_core(addr, clk, cs, data_in, rst, rw, data_out); 617 input [2:0] addr; 618 input clk; 619 input cs; 620 input [7:0] data_in; 621 input rst; 622 input rw; 623 output [7:0] data_out; 624 625 supply1 vdd; 626 supply0 gnd; 627 wire fsm_1_alu_en, net_31, net_68, net_69, net_70, net_143, net_145, net_151; 628 wire net_155, net_159, net_162, net_165, net_207, net_242, net_259, net_260; 629 wire net_261, net_262, net_263, net_264, net_265, net_266, net_267, net_268; 630 wire net_269, net_286, net_287, net_288, net_289, net_290, net_378, net_380; 631 wire net_411, net_416, net_421, net_422, net_425, net_426, net_427, net_428; 632 wire net_429, net_430, net_431, net_474, net_475, net_476, net_477, net_504; 633 wire net_507, net_509, net_510, net_513, net_515, net_539, net_571, net_637; 634 wire net_642, net_646, net_649, net_652, net_668, net_670, net_672, net_674; 635 wire net_676, net_777, net_916, net_1054, net_1084, net_1098, net_1129; 636 wire net_1130, net_1143, net_1147, net_1165; 637 wire [7:3] ioreg5_1_q_opcode; 638 639 memory__bumpallocator bumpallo_0(.clk(clk), .inc_en(net_1143), .rst(rst), 640 .ptr({net_474, net_475, net_476, net_477})); 641 datapath__eq_8bit eq_8bit_0(.a({net_267, net_268, net_269, net_286, net_287, 642 net_288, net_289, net_290}), .b({net_259, net_260, net_261, net_262, 643 net_263, net_264, net_265, net_266}), .eq(net_380)); 644 control__fsm fsm_1(.a(addr[2:0]), .clk(clk), .cs(cs), .op({net_70, net_69, 645 net_68}), .rst(rst), .rw(rw), .alu_en(fsm_1_alu_en), .busy(net_421), 646 .heap_wen(net_31), .q_exec_cdr(net_416), .reg_wen(net_207)); 647 stdcells__inv inv_0(.x(net_70), .y(net_1130)); 648 stdcells__inv inv_1(.x(net_1129), .y(net_1143)); 649 stdcells__inv inv_2(.x(net_1147), .y(net_539)); 650 stdcells__inv inv_3(.x(net_69), .y(net_1165)); 651 memory__ioreg5 ioreg5_1(.a(addr[2:0]), .clk(clk), .data_in(data_in[7:0]), 652 .global_en(cs), .reg_wen(net_207), .result_in({net_165, net_162, net_159, 653 net_242, net_155, net_151, net_145, net_143}), .rst(rst), 654 .status_busy(net_421), .status_carry(net_504), .status_err_heap(net_378), 655 .status_err_type(net_378), .status_zero(net_380), 656 .data_out(data_out[7:0]), .q_arg1({net_267, net_268, net_269, net_286, 657 net_287, net_288, net_289, net_290}), .q_arg2({net_259, net_260, net_261, 658 net_262, net_263, net_264, net_265, net_266}), 659 .q_opcode({ioreg5_1_q_opcode[7], ioreg5_1_q_opcode[6], 660 ioreg5_1_q_opcode[5], ioreg5_1_q_opcode[4], ioreg5_1_q_opcode[3], net_70, 661 net_69, net_68})); 662 stdcells__mux2 mux2_0(.i({net_380, net_571}), .s(net_68), .z(net_1084)); 663 datapath__mux2_8bit mux2_8bi_0(.i0({net_267, net_268, net_269, net_286, 664 net_287, net_288, net_289, net_290}), .i1({net_259, net_260, net_261, 665 net_262, net_263, net_264, net_265, net_266}), .s(net_416), .z({net_676, 666 net_674, net_672, net_670, net_668, net_652, net_649, net_646})); 667 datapath__mux3_4bit mux3_4bi_0(.i0({net_287, net_288, net_289, net_290}), 668 .i1({net_474, net_475, net_476, net_477}), .i2({net_474, net_475, 669 net_476, net_477}), .s({net_416, net_31}), .z({net_411, net_642, net_777, 670 net_637})); 671 datapath__mux4_8bit mux4_8bi_0(.i0({net_431, net_430, net_429, net_428, 672 net_427, net_426, net_425, net_422}), .i1({net_1054, net_1054, net_916, 673 net_916, net_474, net_475, net_476, net_477}), .i2({net_1054, net_916, 674 net_515, net_513, net_510, net_509, net_507, net_1098}), .i3({net_916, 675 net_1084, net_916, net_916, net_916, net_916, net_916, net_1084}), 676 .s({net_70, net_539}), .z({net_165, net_162, net_159, net_242, net_155, 677 net_151, net_145, net_143})); 678 stdcells__nand2 nand2_0(.x(net_268), .y(net_267), .z(net_571)); 679 stdcells__nand2 nand2_1(.x(net_68), .y(net_1165), .z(net_1147)); 680 stdcells__nand3 nand3_0(.w(net_207), .x(net_1130), .y(net_68), 681 .z(net_1129)); 682 datapath__rca_6bit rca_6bit_0(.a({net_269, net_286, net_287, net_288, 683 net_289, net_290}), .b({net_261, net_262, net_263, net_264, net_265, 684 net_266}), .cin(net_916), .cout(net_504), .s({net_515, net_513, net_510, 685 net_509, net_507, net_1098})); 686 memory__regfile16 regfile1_1(.clk(clk), .r_addr({net_287, net_288, net_289, 687 net_290}), .rst(rst), .w_addr({net_411, net_642, net_777, net_637}), 688 .w_data({net_676, net_674, net_672, net_670, net_668, net_652, net_649, 689 net_646}), .w_en(net_31), .r_data({net_431, net_430, net_429, net_428, 690 net_427, net_426, net_425, net_422})); 691 stdcells__tiehigh tiehigh_0(.y(net_1054)); 692 stdcells__tielow tielow_3(.y(net_916)); 693 stdcells__tielow tielow_4(.y(net_378)); 694 endmodule /* chip_core */