lisp_coproc.v (36952B)
1 /* Verilog for cell 'lisp_coproc{lay}' from library 'toplevel' */ 2 /* Created on Thu Dec 04, 2025 22:57:37 */ 3 /* Last revised on Sun Dec 07, 2025 22:49:44 */ 4 /* Written on Mon Dec 08, 2025 19:06:50 by Electric VLSI Design System, version 9.08 */ 5 6 module stdcells__inv(x, y, vdd, gnd); 7 input x; 8 output y; 9 input vdd; 10 input gnd; 11 12 supply1 vdd; 13 supply0 gnd; 14 wire plnode_0_well, plnode_1_well; 15 16 tranif1 nmos_1(gnd, y, x); 17 tranif0 pmos_0(y, vdd, x); 18 endmodule /* stdcells__inv */ 19 20 module stdcells__nand2(x, y, z, vdd, gnd); 21 input x; 22 input y; 23 output z; 24 input vdd; 25 input gnd; 26 27 supply1 vdd; 28 supply0 gnd; 29 wire net_262, plnode_0_well, plnode_1_well; 30 31 tranif1 nmos_1(z, net_262, x); 32 tranif1 nmos_2(net_262, gnd, y); 33 tranif0 pmos_1(vdd, z, y); 34 tranif0 pmos_2(z, vdd, x); 35 endmodule /* stdcells__nand2 */ 36 37 module stdcells__mux2(i, s, z, vdd, gnd); 38 input [1:0] i; 39 input s; 40 output z; 41 input vdd; 42 input gnd; 43 44 supply1 vdd; 45 supply0 gnd; 46 wire net_6, net_8, net_12; 47 48 stdcells__inv inv2_0(.x(s), .y(net_12), .vdd(vdd), .gnd(gnd)); 49 stdcells__nand2 nand2_0(.x(i[1]), .y(s), .z(net_8), .vdd(vdd), .gnd(gnd)); 50 stdcells__nand2 nand2_1(.x(i[0]), .y(net_12), .z(net_6), .vdd(vdd), 51 .gnd(gnd)); 52 stdcells__nand2 nand2_2(.x(net_8), .y(net_6), .z(z), .vdd(vdd), .gnd(gnd)); 53 endmodule /* stdcells__mux2 */ 54 55 module stdcells__tielow(y, vdd, gnd); 56 output y; 57 input vdd; 58 input gnd; 59 60 supply1 vdd; 61 supply0 gnd; 62 wire net_299, plnode_0_well, plnode_1_well; 63 64 tranif1 nmos_0(y, gnd, net_299); 65 tranif0 pmos_1(vdd, net_299); 66 endmodule /* stdcells__tielow */ 67 68 module stdcells__dff(clk, d, rst, q, vdd, gnd); 69 input clk; 70 input d; 71 input rst; 72 output q; 73 input vdd; 74 input gnd; 75 76 supply1 vdd; 77 supply0 gnd; 78 wire net_70, net_71, net_74, net_81, net_83, net_97, net_103; 79 80 stdcells__inv inv_0(.x(clk), .y(net_97), .vdd(vdd), .gnd(gnd)); 81 stdcells__inv inv_1(.x(net_97), .y(net_103), .vdd(vdd), .gnd(gnd)); 82 stdcells__inv inv_2(.x(net_71), .y(net_70), .vdd(vdd), .gnd(gnd)); 83 stdcells__inv inv_3(.x(net_70), .y(q), .vdd(vdd), .gnd(gnd)); 84 stdcells__mux2 mux2_3(.i({net_74, d}), .s(rst), .z(net_81), .vdd(vdd), 85 .gnd(gnd)); 86 stdcells__mux2 mux2_4(.i({net_81, net_83}), .s(net_97), .z(net_83), 87 .vdd(vdd), .gnd(gnd)); 88 stdcells__mux2 mux2_5(.i({net_83, net_71}), .s(net_103), .z(net_71), 89 .vdd(vdd), .gnd(gnd)); 90 stdcells__tielow tielow_1(.y(net_74), .vdd(vdd), .gnd(gnd)); 91 endmodule /* stdcells__dff */ 92 93 module memory__dffe(clk, d, en, rst, q, vdd, gnd); 94 input clk; 95 input d; 96 input en; 97 input rst; 98 output q; 99 input vdd; 100 input gnd; 101 102 supply1 vdd; 103 supply0 gnd; 104 wire net_67; 105 106 stdcells__dff dff_2(.clk(clk), .d(net_67), .rst(rst), .q(q), .vdd(vdd), 107 .gnd(gnd)); 108 stdcells__mux2 mux2_2(.i({d, q}), .s(en), .z(net_67), .vdd(vdd), .gnd(gnd)); 109 endmodule /* memory__dffe */ 110 111 module stdcells__xor2(x, y, z, vdd, gnd); 112 input x; 113 input y; 114 output z; 115 input vdd; 116 input gnd; 117 118 supply1 vdd; 119 supply0 gnd; 120 wire net_355, net_358, net_371; 121 122 stdcells__nand2 n1(.x(x), .y(y), .z(net_355), .vdd(vdd), .gnd(gnd)); 123 stdcells__nand2 n2(.x(x), .y(net_355), .z(net_371), .vdd(vdd), .gnd(gnd)); 124 stdcells__nand2 n3(.x(y), .y(net_355), .z(net_358), .vdd(vdd), .gnd(gnd)); 125 stdcells__nand2 n4(.x(net_371), .y(net_358), .z(z), .vdd(vdd), .gnd(gnd)); 126 endmodule /* stdcells__xor2 */ 127 128 module memory__bumpallocator(clk, rst, inc_en, ptr, vdd, gnd); 129 input clk; 130 input rst; 131 output inc_en; 132 output [3:0] ptr; 133 input vdd; 134 input gnd; 135 136 supply1 vdd; 137 supply0 gnd; 138 wire net_12, net_33, net_35, net_37, net_63; 139 140 memory__dffe dffe_4(.clk(clk), .d(ptr[0]), .en(inc_en), .rst(rst), 141 .q(ptr[0]), .vdd(vdd), .gnd(gnd)); 142 memory__dffe dffe_5(.clk(clk), .d(net_12), .en(inc_en), .rst(rst), 143 .q(ptr[1]), .vdd(vdd), .gnd(gnd)); 144 memory__dffe dffe_6(.clk(clk), .d(net_63), .en(inc_en), .rst(rst), 145 .q(ptr[2]), .vdd(vdd), .gnd(gnd)); 146 memory__dffe dffe_7(.clk(clk), .d(net_37), .en(inc_en), .rst(rst), 147 .q(ptr[3]), .vdd(vdd), .gnd(gnd)); 148 stdcells__inv inv_0(.x(ptr[1]), .y(net_12), .vdd(vdd), .gnd(gnd)); 149 stdcells__inv inv_1(.x(net_33), .y(net_35), .vdd(vdd), .gnd(gnd)); 150 stdcells__nand2 nand2_0(.x(ptr[1]), .y(ptr[2]), .z(net_33), .vdd(vdd), 151 .gnd(gnd)); 152 stdcells__xor2 xor2_0(.x(ptr[2]), .y(ptr[1]), .z(net_63), .vdd(vdd), 153 .gnd(gnd)); 154 stdcells__xor2 xor2_1(.x(ptr[3]), .y(net_35), .z(net_37), .vdd(vdd), 155 .gnd(gnd)); 156 endmodule /* memory__bumpallocator */ 157 158 module stdcells__nor2(x, y, z, vdd, gnd); 159 input x; 160 input y; 161 output z; 162 input vdd; 163 input gnd; 164 165 supply1 vdd; 166 supply0 gnd; 167 wire net_322, plnode_0_well, plnode_1_well; 168 169 tranif1 nmos_1(gnd, z, y); 170 tranif1 nmos_2(z, gnd, x); 171 tranif0 pmos_1(vdd, net_322, x); 172 tranif0 pmos_2(net_322, z, y); 173 endmodule /* stdcells__nor2 */ 174 175 module datapath__eq_8bit(a, b, eq, vdd, gnd); 176 input [7:0] a; 177 input [7:0] b; 178 output eq; 179 input vdd; 180 input gnd; 181 182 supply1 vdd; 183 supply0 gnd; 184 wire net_28, net_30, net_36, net_53, net_57, net_59, net_66, net_70, net_93; 185 wire net_101, net_106, net_116, net_123, net_126; 186 187 stdcells__nand2 nand2_0(.x(net_70), .y(net_106), .z(net_30), .vdd(vdd), 188 .gnd(gnd)); 189 stdcells__nand2 nand2_1(.x(net_36), .y(net_101), .z(net_28), .vdd(vdd), 190 .gnd(gnd)); 191 stdcells__nor2 nor2_0(.x(net_123), .y(net_126), .z(net_70), .vdd(vdd), 192 .gnd(gnd)); 193 stdcells__nor2 nor2_1(.x(net_116), .y(net_93), .z(net_106), .vdd(vdd), 194 .gnd(gnd)); 195 stdcells__nor2 nor2_2(.x(net_66), .y(net_59), .z(net_36), .vdd(vdd), 196 .gnd(gnd)); 197 stdcells__nor2 nor2_3(.x(net_57), .y(net_53), .z(net_101), .vdd(vdd), 198 .gnd(gnd)); 199 stdcells__nor2 nor2_4(.x(net_30), .y(net_28), .z(eq), .vdd(vdd), .gnd(gnd)); 200 stdcells__xor2 xor2_0(.x(a[0]), .y(b[0]), .z(net_123), .vdd(vdd), 201 .gnd(gnd)); 202 stdcells__xor2 xor2_1(.x(a[1]), .y(b[1]), .z(net_126), .vdd(vdd), 203 .gnd(gnd)); 204 stdcells__xor2 xor2_2(.x(a[2]), .y(b[2]), .z(net_116), .vdd(vdd), 205 .gnd(gnd)); 206 stdcells__xor2 xor2_3(.x(a[3]), .y(b[3]), .z(net_93), .vdd(vdd), .gnd(gnd)); 207 stdcells__xor2 xor2_4(.x(a[4]), .y(b[4]), .z(net_66), .vdd(vdd), .gnd(gnd)); 208 stdcells__xor2 xor2_5(.x(a[5]), .y(b[5]), .z(net_59), .vdd(vdd), .gnd(gnd)); 209 stdcells__xor2 xor2_6(.x(a[6]), .y(b[6]), .z(net_57), .vdd(vdd), .gnd(gnd)); 210 stdcells__xor2 xor2_7(.x(a[7]), .y(b[7]), .z(net_53), .vdd(vdd), .gnd(gnd)); 211 endmodule /* datapath__eq_8bit */ 212 213 module stdcells__nand3(w, x, y, z, vdd, gnd); 214 input w; 215 input x; 216 input y; 217 output z; 218 input vdd; 219 input gnd; 220 221 supply1 vdd; 222 supply0 gnd; 223 wire net_262, net_316, plnode_0_well, plnode_1_well; 224 225 tranif1 nmos_1(net_316, net_262, x); 226 tranif1 nmos_2(net_262, gnd, y); 227 tranif1 nmos_3(z, net_316, w); 228 tranif0 pmos_1(vdd, z, y); 229 tranif0 pmos_2(z, vdd, x); 230 tranif0 pmos_4(vdd, z, w); 231 endmodule /* stdcells__nand3 */ 232 233 module control__fsm(a, clk, cs, op, rst, rw, alu_en, busy, heap_wen, 234 q_exec_cdr, reg_wen, vdd, gnd); 235 input [2:0] a; 236 input clk; 237 input cs; 238 input [2:0] op; 239 input rst; 240 input rw; 241 output alu_en; 242 output busy; 243 output heap_wen; 244 output q_exec_cdr; 245 output reg_wen; 246 input vdd; 247 input gnd; 248 249 supply1 vdd; 250 supply0 gnd; 251 wire net_26, net_40, net_43, net_73, net_77, net_88, net_99, net_114, net_116; 252 wire net_128, net_132, net_147, net_159, net_167, net_190, net_200, net_202; 253 wire net_206, net_223, net_225, net_228, net_236, net_397, net_422, net_425; 254 wire net_435; 255 256 stdcells__dff dff_0(.clk(clk), .d(net_159), .rst(rst), .q(net_114), 257 .vdd(vdd), .gnd(gnd)); 258 stdcells__dff dff_1(.clk(clk), .d(net_128), .rst(rst), .q(net_26), .vdd(vdd), 259 .gnd(gnd)); 260 stdcells__dff dff_2(.clk(clk), .d(net_26), .rst(rst), .q(alu_en), .vdd(vdd), 261 .gnd(gnd)); 262 stdcells__dff dff_3(.clk(clk), .d(net_206), .rst(rst), .q(q_exec_cdr), 263 .vdd(vdd), .gnd(gnd)); 264 stdcells__dff dff_4(.clk(clk), .d(net_228), .rst(rst), .q(reg_wen), 265 .vdd(vdd), .gnd(gnd)); 266 stdcells__inv inv_0(.x(rw), .y(net_99), .vdd(vdd), .gnd(gnd)); 267 stdcells__inv inv_1(.x(a[0]), .y(net_88), .vdd(vdd), .gnd(gnd)); 268 stdcells__inv inv_2(.x(a[1]), .y(net_73), .vdd(vdd), .gnd(gnd)); 269 stdcells__inv inv_3(.x(a[2]), .y(net_77), .vdd(vdd), .gnd(gnd)); 270 stdcells__inv inv_4(.x(net_397), .y(net_128), .vdd(vdd), .gnd(gnd)); 271 stdcells__inv inv_5(.x(net_116), .y(net_132), .vdd(vdd), .gnd(gnd)); 272 stdcells__inv inv_6(.x(reg_wen), .y(net_147), .vdd(vdd), .gnd(gnd)); 273 stdcells__inv inv_7(.x(alu_en), .y(net_200), .vdd(vdd), .gnd(gnd)); 274 stdcells__inv inv_8(.x(q_exec_cdr), .y(net_223), .vdd(vdd), .gnd(gnd)); 275 stdcells__inv inv_9(.x(net_236), .y(heap_wen), .vdd(vdd), .gnd(gnd)); 276 stdcells__inv inv_10(.x(net_114), .y(busy), .vdd(vdd), .gnd(gnd)); 277 stdcells__nand2 nand2_3(.x(net_88), .y(net_73), .z(net_43), .vdd(vdd), 278 .gnd(gnd)); 279 stdcells__nand2 nand2_4(.x(net_116), .y(net_114), .z(net_397), .vdd(vdd), 280 .gnd(gnd)); 281 stdcells__nand2 nand2_5(.x(net_132), .y(net_114), .z(net_435), .vdd(vdd), 282 .gnd(gnd)); 283 stdcells__nand2 nand2_6(.x(net_425), .y(net_422), .z(net_167), .vdd(vdd), 284 .gnd(gnd)); 285 stdcells__nand2 nand2_7(.x(op[0]), .y(net_190), .z(net_202), .vdd(vdd), 286 .gnd(gnd)); 287 stdcells__nand2 nand2_8(.x(net_202), .y(alu_en), .z(net_225), .vdd(vdd), 288 .gnd(gnd)); 289 stdcells__nand2 nand2_9(.x(net_225), .y(net_223), .z(net_228), .vdd(vdd), 290 .gnd(gnd)); 291 stdcells__nand3 nand3_0(.w(cs), .x(net_99), .y(net_77), .z(net_40), 292 .vdd(vdd), .gnd(gnd)); 293 stdcells__nand3 nand3_1(.w(net_435), .x(net_147), .y(net_167), .z(net_159), 294 .vdd(vdd), .gnd(gnd)); 295 stdcells__nor2 nor2_0(.x(reg_wen), .y(alu_en), .z(net_425), .vdd(vdd), 296 .gnd(gnd)); 297 stdcells__nor2 nor2_1(.x(net_26), .y(net_114), .z(net_422), .vdd(vdd), 298 .gnd(gnd)); 299 stdcells__nor2 nor2_2(.x(op[1]), .y(op[2]), .z(net_190), .vdd(vdd), 300 .gnd(gnd)); 301 stdcells__nor2 nor2_3(.x(net_200), .y(net_202), .z(net_206), .vdd(vdd), 302 .gnd(gnd)); 303 stdcells__nor2 nor2_4(.x(net_206), .y(q_exec_cdr), .z(net_236), .vdd(vdd), 304 .gnd(gnd)); 305 stdcells__nor2 nor2_5(.x(net_40), .y(net_43), .z(net_116), .vdd(vdd), 306 .gnd(gnd)); 307 endmodule /* control__fsm */ 308 309 module stdcells__dec2(a0, a1, en, _q0, _q1, _q2, _q3, vdd, gnd); 310 input a0; 311 input a1; 312 input en; 313 output _q0; 314 output _q1; 315 output _q2; 316 output _q3; 317 input vdd; 318 input gnd; 319 320 supply1 vdd; 321 supply0 gnd; 322 wire net_88, net_92; 323 324 stdcells__inv inv_1(.x(a0), .y(net_88), .vdd(vdd), .gnd(gnd)); 325 stdcells__inv inv_2(.x(a1), .y(net_92), .vdd(vdd), .gnd(gnd)); 326 stdcells__nand3 nand3_0(.w(net_88), .x(net_92), .y(en), .z(_q0), .vdd(vdd), 327 .gnd(gnd)); 328 stdcells__nand3 nand3_1(.w(net_88), .x(a1), .y(en), .z(_q1), .vdd(vdd), 329 .gnd(gnd)); 330 stdcells__nand3 nand3_2(.w(a0), .x(net_92), .y(en), .z(_q2), .vdd(vdd), 331 .gnd(gnd)); 332 stdcells__nand3 nand3_3(.w(a0), .x(a1), .y(en), .z(_q3), .vdd(vdd), 333 .gnd(gnd)); 334 endmodule /* stdcells__dec2 */ 335 336 module datapath__mux2_8bit(i0, i1, s, z, vdd, gnd); 337 input [7:0] i0; 338 input [7:0] i1; 339 input s; 340 input [7:0] z; 341 input vdd; 342 input gnd; 343 344 supply1 vdd; 345 supply0 gnd; 346 stdcells__mux2 mux2_0_(.i({i1[0], i0[0]}), .s(s), .z(z[0]), .vdd(vdd), 347 .gnd(gnd)); 348 stdcells__mux2 mux2_1_(.i({i1[1], i0[1]}), .s(s), .z(z[1]), .vdd(vdd), 349 .gnd(gnd)); 350 stdcells__mux2 mux2_2_(.i({i1[2], i0[2]}), .s(s), .z(z[2]), .vdd(vdd), 351 .gnd(gnd)); 352 stdcells__mux2 mux2_3_(.i({i1[3], i0[3]}), .s(s), .z(z[3]), .vdd(vdd), 353 .gnd(gnd)); 354 stdcells__mux2 mux2_4_(.i({i1[4], i0[4]}), .s(s), .z(z[4]), .vdd(vdd), 355 .gnd(gnd)); 356 stdcells__mux2 mux2_5_(.i({i1[5], i0[5]}), .s(s), .z(z[5]), .vdd(vdd), 357 .gnd(gnd)); 358 stdcells__mux2 mux2_6_(.i({i1[6], i0[6]}), .s(s), .z(z[6]), .vdd(vdd), 359 .gnd(gnd)); 360 stdcells__mux2 mux2_7_(.i({i1[7], i0[7]}), .s(s), .z(z[7]), .vdd(vdd), 361 .gnd(gnd)); 362 endmodule /* datapath__mux2_8bit */ 363 364 module datapath__mux4(i, s, z, vdd, gnd); 365 input [3:0] i; 366 input [1:0] s; 367 output z; 368 input vdd; 369 input gnd; 370 371 supply1 vdd; 372 supply0 gnd; 373 wire net_4, net_7; 374 375 stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_7), .vdd(vdd), 376 .gnd(gnd)); 377 stdcells__mux2 mux2_1(.i(i[3:2]), .s(s[0]), .z(net_4), .vdd(vdd), 378 .gnd(gnd)); 379 stdcells__mux2 mux2_2(.i({net_4, net_7}), .s(s[1]), .z(z), .vdd(vdd), 380 .gnd(gnd)); 381 endmodule /* datapath__mux4 */ 382 383 module datapath__mux4_8bit(i0, i1, i2, i3, s, z, vdd, gnd); 384 input [7:0] i0; 385 input [7:0] i1; 386 input [7:0] i2; 387 input [7:0] i3; 388 input [1:0] s; 389 output [7:0] z; 390 input vdd; 391 input gnd; 392 393 supply1 vdd; 394 supply0 gnd; 395 datapath__mux4 mux4_0(.i({i3[7], i2[7], i1[7], i0[7]}), .s(s[1:0]), .z(z[7]), 396 .vdd(vdd), .gnd(gnd)); 397 datapath__mux4 mux4_1(.i({i3[6], i2[6], i1[6], i0[6]}), .s(s[1:0]), .z(z[6]), 398 .vdd(vdd), .gnd(gnd)); 399 datapath__mux4 mux4_2(.i({i3[5], i2[5], i1[5], i0[5]}), .s(s[1:0]), .z(z[5]), 400 .vdd(vdd), .gnd(gnd)); 401 datapath__mux4 mux4_3(.i({i3[4], i2[4], i1[4], i0[4]}), .s(s[1:0]), .z(z[4]), 402 .vdd(vdd), .gnd(gnd)); 403 datapath__mux4 mux4_4(.i({i3[3], i2[3], i1[3], i0[3]}), .s(s[1:0]), .z(z[3]), 404 .vdd(vdd), .gnd(gnd)); 405 datapath__mux4 mux4_5(.i({i3[2], i2[2], i1[2], i0[2]}), .s(s[1:0]), .z(z[2]), 406 .vdd(vdd), .gnd(gnd)); 407 datapath__mux4 mux4_6(.i({i3[1], i2[1], i1[1], i0[1]}), .s(s[1:0]), .z(z[1]), 408 .vdd(vdd), .gnd(gnd)); 409 datapath__mux4 mux4_7(.i({i3[0], i2[0], i1[0], i0[0]}), .s(s[1:0]), .z(z[0]), 410 .vdd(vdd), .gnd(gnd)); 411 endmodule /* datapath__mux4_8bit */ 412 413 module memory__reg8(clk, d, en, rst, q, vdd, gnd); 414 input clk; 415 input [7:0] d; 416 input en; 417 input rst; 418 output [7:0] q; 419 input vdd; 420 input gnd; 421 422 supply1 vdd; 423 supply0 gnd; 424 memory__dffe dffe_8(.clk(clk), .d(d[7]), .en(en), .rst(rst), .q(q[7]), 425 .vdd(vdd), .gnd(gnd)); 426 memory__dffe dffe_9(.clk(clk), .d(d[6]), .en(en), .rst(rst), .q(q[6]), 427 .vdd(vdd), .gnd(gnd)); 428 memory__dffe dffe_10(.clk(clk), .d(d[5]), .en(en), .rst(rst), .q(q[5]), 429 .vdd(vdd), .gnd(gnd)); 430 memory__dffe dffe_11(.clk(clk), .d(d[4]), .en(en), .rst(rst), .q(q[4]), 431 .vdd(vdd), .gnd(gnd)); 432 memory__dffe dffe_12(.clk(clk), .d(d[3]), .en(en), .rst(rst), .q(q[3]), 433 .vdd(vdd), .gnd(gnd)); 434 memory__dffe dffe_13(.clk(clk), .d(d[2]), .en(en), .rst(rst), .q(q[2]), 435 .vdd(vdd), .gnd(gnd)); 436 memory__dffe dffe_14(.clk(clk), .d(d[1]), .en(en), .rst(rst), .q(q[1]), 437 .vdd(vdd), .gnd(gnd)); 438 memory__dffe dffe_15(.clk(clk), .d(d[0]), .en(en), .rst(rst), .q(q[0]), 439 .vdd(vdd), .gnd(gnd)); 440 endmodule /* memory__reg8 */ 441 442 module stdcells__tiehigh(y, vdd, gnd); 443 output y; 444 input vdd; 445 input gnd; 446 447 supply1 vdd; 448 supply0 gnd; 449 wire net_299, plnode_0_well, plnode_1_well; 450 451 tranif1 nmos_0(gnd, net_299); 452 tranif0 pmos_1(vdd, y, net_299); 453 endmodule /* stdcells__tiehigh */ 454 455 module memory__ioreg5(a, clk, data_in, data_out, global_en, reg_wen, result_in, 456 rst, status_busy, status_carry, status_err_heap, status_err_type, 457 status_zero, data_out_1, q_arg1, q_arg2, q_opcode, gnd, vdd); 458 input [2:0] a; 459 input clk; 460 input [7:0] data_in; 461 input [0:0] data_out; 462 input global_en; 463 input reg_wen; 464 input [7:0] result_in; 465 input rst; 466 input status_busy; 467 input status_carry; 468 input status_err_heap; 469 input status_err_type; 470 input status_zero; 471 output [7:1] data_out_1; 472 output [7:0] q_arg1; 473 output [7:0] q_arg2; 474 output [7:0] q_opcode; 475 input gnd; 476 input vdd; 477 478 supply1 vdd; 479 wire net_2, net_8, net_12, net_18, net_50, net_51, net_53, net_55, net_57; 480 wire net_61, net_63, net_67, net_87, net_90, net_96, net_98, net_100, net_102; 481 wire net_194, net_195, net_196, net_197, net_198, net_199, net_200, net_473; 482 wire net_476, net_477, net_481, net_487, net_527, net_534, net_543, net_551; 483 wire net_555, net_556, net_557, net_558, net_559, net_560, net_561, net_562; 484 wire net_791, net_797, net_826, net_828, net_832; 485 486 stdcells__dec2 dec2_0(.a0(a[0]), .a1(a[1]), .en(net_826), ._q0(net_96), 487 ._q1(net_98), ._q2(net_100), ._q3(net_102), .vdd(vdd), .gnd(gnd)); 488 stdcells__inv inv_0(.x(net_90), .y(net_18), .vdd(vdd), .gnd(gnd)); 489 stdcells__inv inv_1(.x(net_100), .y(net_12), .vdd(vdd), .gnd(gnd)); 490 stdcells__inv inv_2(.x(net_98), .y(net_8), .vdd(vdd), .gnd(gnd)); 491 stdcells__inv inv_3(.x(net_96), .y(net_2), .vdd(vdd), .gnd(gnd)); 492 stdcells__inv inv_4(.x(net_102), .y(net_87), .vdd(vdd), .gnd(gnd)); 493 stdcells__inv inv_5(.x(a[2]), .y(net_832), .vdd(vdd), .gnd(gnd)); 494 stdcells__inv inv_6(.x(net_828), .y(net_826), .vdd(vdd), .gnd(gnd)); 495 datapath__mux2_8bit mux2_8bi_0(.i0(data_in[7:0]), .i1(result_in[7:0]), 496 .s(reg_wen), .z({net_63, net_67, net_61, net_57, net_55, net_53, net_51, 497 net_50}), .vdd(vdd), .gnd(gnd)); 498 datapath__mux2_8bit mux2_8bi_1(.i0({net_473, net_477, net_476, net_551, 499 net_543, net_534, net_487, net_481}), .i1({net_555, net_556, net_557, 500 net_558, net_559, net_560, net_561, net_562}), .s(a[2]), 501 .z({data_out_1[7], data_out_1[6], data_out_1[5], data_out_1[4], 502 data_out_1[3], data_out_1[2], data_out_1[1], data_out[0]}), .vdd(vdd), 503 .gnd(gnd)); 504 datapath__mux4_8bit mux4_8bi_0(.i0(q_opcode[7:0]), .i1(q_arg1[7:0]), 505 .i2(q_arg2[7:0]), .i3({net_200, net_199, net_198, net_197, net_196, 506 net_195, net_194, net_527}), .s(a[1:0]), .z({net_473, net_477, net_476, 507 net_551, net_543, net_534, net_487, net_481}), .vdd(vdd), .gnd(gnd)); 508 stdcells__nand2 nand2_0(.x(net_832), .y(global_en), .z(net_828), .vdd(vdd), 509 .gnd(gnd)); 510 stdcells__nor2 nor2_0(.x(reg_wen), .y(net_87), .z(net_90), .vdd(vdd), 511 .gnd(gnd)); 512 memory__reg8 reg8_0(.clk(clk), .d({net_791, net_791, net_791, status_zero, 513 status_carry, status_err_type, status_err_heap, status_busy}), 514 .en(net_797), .rst(rst), .q({net_555, net_556, net_557, net_558, net_559, 515 net_560, net_561, net_562}), .vdd(vdd), .gnd(gnd)); 516 memory__reg8 reg8_1(.clk(clk), .d({net_63, net_67, net_61, net_57, net_55, 517 net_53, net_51, net_50}), .en(net_18), .rst(rst), .q({net_200, net_199, 518 net_198, net_197, net_196, net_195, net_194, net_527}), .vdd(vdd), 519 .gnd(gnd)); 520 memory__reg8 reg8_2(.clk(clk), .d(data_in[7:0]), .en(net_12), .rst(rst), 521 .q(q_arg2[7:0]), .vdd(vdd), .gnd(gnd)); 522 memory__reg8 reg8_3(.clk(clk), .d(data_in[7:0]), .en(net_8), .rst(rst), 523 .q(q_arg1[7:0]), .vdd(vdd), .gnd(gnd)); 524 memory__reg8 reg8_4(.clk(clk), .d(data_in[7:0]), .en(net_2), .rst(rst), 525 .q(q_opcode[7:0]), .vdd(vdd), .gnd(gnd)); 526 stdcells__tiehigh tiehigh_0(.y(net_797), .vdd(vdd), .gnd(gnd)); 527 stdcells__tielow tielow_0(.y(net_791), .vdd(vdd), .gnd(gnd)); 528 endmodule /* memory__ioreg5 */ 529 530 module datapath__mux3(i, s, z, vdd, gnd, i_1); 531 input [1:0] i; 532 input [1:0] s; 533 output z; 534 input vdd; 535 input gnd; 536 input [2:2] i_1; 537 538 supply1 vdd; 539 supply0 gnd; 540 wire net_2; 541 542 stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_2), .vdd(vdd), 543 .gnd(gnd)); 544 stdcells__mux2 mux2_1(.i({i_1[2], net_2}), .s(s[1]), .z(z), .vdd(vdd), 545 .gnd(gnd)); 546 endmodule /* datapath__mux3 */ 547 548 module datapath__mux3_4bit(i0, i1, i2, s, z, vdd, gnd); 549 input [3:0] i0; 550 input [3:0] i1; 551 input [3:0] i2; 552 input [1:0] s; 553 output [3:0] z; 554 input vdd; 555 input gnd; 556 557 supply1 vdd; 558 supply0 gnd; 559 datapath__mux3 mux3_0(.i({i1[3], i0[3]}), .s(s[1:0]), .z(z[3]), .vdd(vdd), 560 .gnd(gnd), .i_1(i2[3:3])); 561 datapath__mux3 mux3_1(.i({i1[2], i0[2]}), .s(s[1:0]), .z(z[2]), .vdd(vdd), 562 .gnd(gnd), .i_1(i2[2:2])); 563 datapath__mux3 mux3_2(.i({i1[1], i0[1]}), .s(s[1:0]), .z(z[1]), .vdd(vdd), 564 .gnd(gnd), .i_1(i2[1:1])); 565 datapath__mux3 mux3_3(.i({i1[0], i0[0]}), .s(s[1:0]), .z(z[0]), .vdd(vdd), 566 .gnd(gnd), .i_1(i2[0:0])); 567 endmodule /* datapath__mux3_4bit */ 568 569 module stdcells__fa(a, b, cin, cout, s, vdd, gnd); 570 input a; 571 input b; 572 input cin; 573 output cout; 574 output s; 575 input vdd; 576 input gnd; 577 578 supply1 vdd; 579 supply0 gnd; 580 wire net_10; 581 582 stdcells__mux2 mux2_1(.i({cin, a}), .s(net_10), .z(cout), .vdd(vdd), 583 .gnd(gnd)); 584 stdcells__xor2 xor2_0(.x(a), .y(b), .z(net_10), .vdd(vdd), .gnd(gnd)); 585 stdcells__xor2 xor2_1(.x(net_10), .y(cin), .z(s), .vdd(vdd), .gnd(gnd)); 586 endmodule /* stdcells__fa */ 587 588 module datapath__rca_6bit(a, b, cin, cout, s, vdd, gnd); 589 input [5:0] a; 590 input [5:0] b; 591 input cin; 592 output cout; 593 output [5:0] s; 594 input vdd; 595 input gnd; 596 597 supply1 vdd; 598 supply0 gnd; 599 wire net_147, net_148, net_149, net_150, net_151; 600 601 stdcells__fa fa_14(.a(a[0]), .b(b[0]), .cin(cin), .cout(net_148), .s(s[0]), 602 .vdd(vdd), .gnd(gnd)); 603 stdcells__fa fa_15(.a(a[1]), .b(b[1]), .cin(net_148), .cout(net_147), 604 .s(s[1]), .vdd(vdd), .gnd(gnd)); 605 stdcells__fa fa_16(.a(a[2]), .b(b[2]), .cin(net_147), .cout(net_149), 606 .s(s[2]), .vdd(vdd), .gnd(gnd)); 607 stdcells__fa fa_17(.a(a[3]), .b(b[3]), .cin(net_149), .cout(net_150), 608 .s(s[3]), .vdd(vdd), .gnd(gnd)); 609 stdcells__fa fa_18(.a(a[4]), .b(b[4]), .cin(net_150), .cout(net_151), 610 .s(s[4]), .vdd(vdd), .gnd(gnd)); 611 stdcells__fa fa_19(.a(a[5]), .b(b[5]), .cin(net_151), .cout(cout), .s(s[5]), 612 .vdd(vdd), .gnd(gnd)); 613 endmodule /* datapath__rca_6bit */ 614 615 module memory__dec4(a, en, q, vdd, gnd); 616 input [3:0] a; 617 input en; 618 output [15:0] q; 619 input vdd; 620 input gnd; 621 622 supply1 vdd; 623 supply0 gnd; 624 wire net_55, net_61, net_73, net_81, net_89, net_96, net_100, net_104; 625 626 stdcells__dec2 dec2_1(.a0(a[3]), .a1(a[2]), .en(en), ._q0(net_96), 627 ._q1(net_100), ._q2(net_104), ._q3(net_89), .vdd(vdd), .gnd(gnd)); 628 stdcells__dec2 dec2_2(.a0(a[1]), .a1(a[0]), .en(en), ._q0(net_55), 629 ._q1(net_61), ._q2(net_81), ._q3(net_73), .vdd(vdd), .gnd(gnd)); 630 stdcells__nor2 nor2_8(.x(net_96), .y(net_55), .z(q[0]), .vdd(vdd), 631 .gnd(gnd)); 632 stdcells__nor2 nor2_9(.x(net_96), .y(net_61), .z(q[1]), .vdd(vdd), 633 .gnd(gnd)); 634 stdcells__nor2 nor2_10(.x(net_96), .y(net_81), .z(q[2]), .vdd(vdd), 635 .gnd(gnd)); 636 stdcells__nor2 nor2_11(.x(net_96), .y(net_73), .z(q[3]), .vdd(vdd), 637 .gnd(gnd)); 638 stdcells__nor2 nor2_12(.x(net_100), .y(net_55), .z(q[4]), .vdd(vdd), 639 .gnd(gnd)); 640 stdcells__nor2 nor2_13(.x(net_100), .y(net_61), .z(q[5]), .vdd(vdd), 641 .gnd(gnd)); 642 stdcells__nor2 nor2_14(.x(net_100), .y(net_81), .z(q[6]), .vdd(vdd), 643 .gnd(gnd)); 644 stdcells__nor2 nor2_15(.x(net_100), .y(net_73), .z(q[7]), .vdd(vdd), 645 .gnd(gnd)); 646 stdcells__nor2 nor2_16(.x(net_104), .y(net_55), .z(q[8]), .vdd(vdd), 647 .gnd(gnd)); 648 stdcells__nor2 nor2_17(.x(net_104), .y(net_61), .z(q[9]), .vdd(vdd), 649 .gnd(gnd)); 650 stdcells__nor2 nor2_18(.x(net_104), .y(net_81), .z(q[10]), .vdd(vdd), 651 .gnd(gnd)); 652 stdcells__nor2 nor2_19(.x(net_104), .y(net_73), .z(q[11]), .vdd(vdd), 653 .gnd(gnd)); 654 stdcells__nor2 nor2_20(.x(net_89), .y(net_55), .z(q[12]), .vdd(vdd), 655 .gnd(gnd)); 656 stdcells__nor2 nor2_21(.x(net_89), .y(net_61), .z(q[13]), .vdd(vdd), 657 .gnd(gnd)); 658 stdcells__nor2 nor2_22(.x(net_89), .y(net_81), .z(q[14]), .vdd(vdd), 659 .gnd(gnd)); 660 stdcells__nor2 nor2_23(.x(net_89), .y(net_73), .z(q[15]), .vdd(vdd), 661 .gnd(gnd)); 662 endmodule /* memory__dec4 */ 663 664 module memory__mux16(i, s, z, vdd, gnd); 665 input [15:0] i; 666 input [3:0] s; 667 output z; 668 input vdd; 669 input gnd; 670 671 supply1 vdd; 672 supply0 gnd; 673 wire net_174, net_176, net_179, net_182, net_184, net_186, net_188, net_190; 674 wire net_193, net_195, net_199, net_201, net_204, net_206; 675 676 stdcells__mux2 mux2_0(.i({i[14], i[15]}), .s(s[0]), .z(net_201), .vdd(vdd), 677 .gnd(gnd)); 678 stdcells__mux2 mux2_2(.i(i[13:12]), .s(s[0]), .z(net_199), .vdd(vdd), 679 .gnd(gnd)); 680 stdcells__mux2 mux2_3(.i({i[10], i[11]}), .s(s[0]), .z(net_195), .vdd(vdd), 681 .gnd(gnd)); 682 stdcells__mux2 mux2_4(.i(i[9:8]), .s(s[0]), .z(net_193), .vdd(vdd), 683 .gnd(gnd)); 684 stdcells__mux2 mux2_5(.i({i[6], i[7]}), .s(s[0]), .z(net_204), .vdd(vdd), 685 .gnd(gnd)); 686 stdcells__mux2 mux2_6(.i(i[5:4]), .s(s[0]), .z(net_206), .vdd(vdd), 687 .gnd(gnd)); 688 stdcells__mux2 mux2_7(.i({i[2], i[3]}), .s(s[0]), .z(net_190), .vdd(vdd), 689 .gnd(gnd)); 690 stdcells__mux2 mux2_8(.i(i[1:0]), .s(s[0]), .z(net_188), .vdd(vdd), 691 .gnd(gnd)); 692 stdcells__mux2 mux2_9(.i({net_201, net_199}), .s(s[1]), .z(net_186), 693 .vdd(vdd), .gnd(gnd)); 694 stdcells__mux2 mux2_10(.i({net_195, net_193}), .s(s[1]), .z(net_184), 695 .vdd(vdd), .gnd(gnd)); 696 stdcells__mux2 mux2_11(.i({net_204, net_206}), .s(s[1]), .z(net_182), 697 .vdd(vdd), .gnd(gnd)); 698 stdcells__mux2 mux2_12(.i({net_190, net_188}), .s(s[1]), .z(net_179), 699 .vdd(vdd), .gnd(gnd)); 700 stdcells__mux2 mux2_15(.i({net_182, net_179}), .s(s[2]), .z(net_174), 701 .vdd(vdd), .gnd(gnd)); 702 stdcells__mux2 mux2_16(.i({net_186, net_184}), .s(s[2]), .z(net_176), 703 .vdd(vdd), .gnd(gnd)); 704 stdcells__mux2 mux2_17(.i({net_176, net_174}), .s(s[3]), .z(z), .vdd(vdd), 705 .gnd(gnd)); 706 endmodule /* memory__mux16 */ 707 708 module memory__regfile16(clk, r_addr, rst, w_addr, w_data, w_en, r_data, vdd, 709 gnd); 710 input clk; 711 input [3:0] r_addr; 712 input rst; 713 input [3:0] w_addr; 714 input [7:0] w_data; 715 input w_en; 716 output [7:0] r_data; 717 input vdd; 718 input gnd; 719 720 supply1 vdd; 721 supply0 gnd; 722 wire net_718, net_720, net_723, net_725, net_731, net_732, net_733, net_734; 723 wire net_750, net_751, net_754, net_756, net_758, net_760, net_765, net_778; 724 wire net_812, net_814, net_818, net_819, net_820, net_821, net_822, net_823; 725 wire net_824, net_825, net_826, net_827, net_828, net_829, net_830, net_831; 726 wire net_860, net_861, net_862, net_863, net_864, net_865, net_866, net_867; 727 wire net_868, net_869, net_870, net_871, net_872, net_873, net_874, net_875; 728 wire net_908, net_909, net_910, net_911, net_912, net_914, net_915, net_916; 729 wire net_917, net_918, net_919, net_920, net_921, net_922, net_923, net_924; 730 wire net_925, net_926, net_927, net_928, net_929, net_930, net_931, net_932; 731 wire net_933, net_934, net_935, net_936, net_937, net_938, net_939, net_940; 732 wire net_941, net_942, net_943, net_944, net_945, net_946, net_947, net_948; 733 wire net_949, net_950, net_951, net_952, net_953, net_954, net_955, net_956; 734 wire net_957, net_958, net_959, net_960, net_961, net_962, net_963, net_964; 735 wire net_965, net_966, net_967, net_968, net_969, net_970, net_971, net_972; 736 wire net_973, net_974, net_975, net_976, net_977, net_978, net_979, net_980; 737 wire net_981, net_982, net_983, net_984, net_985, net_986, net_987, net_988; 738 wire net_989, net_990, net_991, net_992, net_993, net_994, net_995, net_996; 739 wire net_997, net_998, net_999, net_1000, net_1001, net_1002, net_1003; 740 wire net_1916; 741 742 memory__dec4 dec4_0(.a(w_addr[3:0]), .en(w_en), .q({net_750, net_751, 743 net_754, net_756, net_758, net_760, net_765, net_778, net_734, net_733, 744 net_732, net_731, net_725, net_723, net_720, net_718}), .vdd(vdd), 745 .gnd(gnd)); 746 memory__mux16 mux16_0(.i({net_875, net_874, net_873, net_872, net_871, 747 net_870, net_869, net_868, net_867, net_866, net_865, net_864, net_863, 748 net_862, net_861, net_860}), .s(r_addr[3:0]), .z(r_data[7]), .vdd(vdd), 749 .gnd(gnd)); 750 memory__mux16 mux16_1(.i({net_831, net_830, net_829, net_828, net_827, 751 net_826, net_825, net_824, net_823, net_822, net_821, net_820, net_819, 752 net_818, net_814, net_812}), .s(r_addr[3:0]), .z(r_data[6]), .vdd(vdd), 753 .gnd(gnd)); 754 memory__mux16 mux16_2(.i({net_923, net_922, net_921, net_920, net_919, 755 net_918, net_917, net_916, net_915, net_914, net_1916, net_912, net_911, 756 net_910, net_909, net_908}), .s(r_addr[3:0]), .z(r_data[5]), .vdd(vdd), 757 .gnd(gnd)); 758 memory__mux16 mux16_3(.i({net_939, net_938, net_937, net_936, net_935, 759 net_934, net_933, net_932, net_931, net_930, net_929, net_928, net_927, 760 net_926, net_925, net_924}), .s(r_addr[3:0]), .z(r_data[4]), .vdd(vdd), 761 .gnd(gnd)); 762 memory__mux16 mux16_4(.i({net_955, net_954, net_953, net_952, net_951, 763 net_950, net_949, net_948, net_947, net_946, net_945, net_944, net_943, 764 net_942, net_941, net_940}), .s(r_addr[3:0]), .z(r_data[3]), .vdd(vdd), 765 .gnd(gnd)); 766 memory__mux16 mux16_5(.i({net_971, net_970, net_969, net_968, net_967, 767 net_966, net_965, net_964, net_963, net_962, net_961, net_960, net_959, 768 net_958, net_957, net_956}), .s(r_addr[3:0]), .z(r_data[2]), .vdd(vdd), 769 .gnd(gnd)); 770 memory__mux16 mux16_6(.i({net_987, net_986, net_985, net_984, net_983, 771 net_982, net_981, net_980, net_979, net_978, net_977, net_976, net_975, 772 net_974, net_973, net_972}), .s(r_addr[3:0]), .z(r_data[1]), .vdd(vdd), 773 .gnd(gnd)); 774 memory__mux16 mux16_7(.i({net_1003, net_1002, net_1001, net_1000, net_999, 775 net_998, net_997, net_996, net_995, net_994, net_993, net_992, net_991, 776 net_990, net_989, net_988}), .s(r_addr[3:0]), .z(r_data[0]), .vdd(vdd), 777 .gnd(gnd)); 778 memory__reg8 reg8_0(.clk(clk), .d(w_data[7:0]), .en(net_750), .rst(rst), 779 .q({net_875, net_831, net_923, net_939, net_955, net_971, net_987, 780 net_1003}), .vdd(vdd), .gnd(gnd)); 781 memory__reg8 reg8_1(.clk(clk), .d(w_data[7:0]), .en(net_751), .rst(rst), 782 .q({net_874, net_830, net_922, net_938, net_954, net_970, net_986, 783 net_1002}), .vdd(vdd), .gnd(gnd)); 784 memory__reg8 reg8_2(.clk(clk), .d(w_data[7:0]), .en(net_754), .rst(rst), 785 .q({net_873, net_829, net_921, net_937, net_953, net_969, net_985, 786 net_1001}), .vdd(vdd), .gnd(gnd)); 787 memory__reg8 reg8_3(.clk(clk), .d(w_data[7:0]), .en(net_756), .rst(rst), 788 .q({net_872, net_828, net_920, net_936, net_952, net_968, net_984, 789 net_1000}), .vdd(vdd), .gnd(gnd)); 790 memory__reg8 reg8_4(.clk(clk), .d(w_data[7:0]), .en(net_758), .rst(rst), 791 .q({net_871, net_827, net_919, net_935, net_951, net_967, net_983, 792 net_999}), .vdd(vdd), .gnd(gnd)); 793 memory__reg8 reg8_5(.clk(clk), .d(w_data[7:0]), .en(net_760), .rst(rst), 794 .q({net_870, net_826, net_918, net_934, net_950, net_966, net_982, 795 net_998}), .vdd(vdd), .gnd(gnd)); 796 memory__reg8 reg8_6(.clk(clk), .d(w_data[7:0]), .en(net_765), .rst(rst), 797 .q({net_869, net_825, net_917, net_933, net_949, net_965, net_981, 798 net_997}), .vdd(vdd), .gnd(gnd)); 799 memory__reg8 reg8_7(.clk(clk), .d(w_data[7:0]), .en(net_778), .rst(rst), 800 .q({net_868, net_824, net_916, net_932, net_948, net_964, net_980, 801 net_996}), .vdd(vdd), .gnd(gnd)); 802 memory__reg8 reg8_8(.clk(clk), .d(w_data[7:0]), .en(net_734), .rst(rst), 803 .q({net_867, net_823, net_915, net_931, net_947, net_963, net_979, 804 net_995}), .vdd(vdd), .gnd(gnd)); 805 memory__reg8 reg8_9(.clk(clk), .d(w_data[7:0]), .en(net_733), .rst(rst), 806 .q({net_866, net_822, net_914, net_930, net_946, net_962, net_978, 807 net_994}), .vdd(vdd), .gnd(gnd)); 808 memory__reg8 reg8_10(.clk(clk), .d(w_data[7:0]), .en(net_732), .rst(rst), 809 .q({net_865, net_821, net_1916, net_929, net_945, net_961, net_977, 810 net_993}), .vdd(vdd), .gnd(gnd)); 811 memory__reg8 reg8_11(.clk(clk), .d(w_data[7:0]), .en(net_731), .rst(rst), 812 .q({net_864, net_820, net_912, net_928, net_944, net_960, net_976, 813 net_992}), .vdd(vdd), .gnd(gnd)); 814 memory__reg8 reg8_12(.clk(clk), .d(w_data[7:0]), .en(net_725), .rst(rst), 815 .q({net_863, net_819, net_911, net_927, net_943, net_959, net_975, 816 net_991}), .vdd(vdd), .gnd(gnd)); 817 memory__reg8 reg8_13(.clk(clk), .d(w_data[7:0]), .en(net_723), .rst(rst), 818 .q({net_862, net_818, net_910, net_926, net_942, net_958, net_974, 819 net_990}), .vdd(vdd), .gnd(gnd)); 820 memory__reg8 reg8_14(.clk(clk), .d(w_data[7:0]), .en(net_720), .rst(rst), 821 .q({net_861, net_814, net_909, net_925, net_941, net_957, net_973, 822 net_989}), .vdd(vdd), .gnd(gnd)); 823 memory__reg8 reg8_15(.clk(clk), .d(w_data[7:0]), .en(net_718), .rst(rst), 824 .q({net_860, net_812, net_908, net_924, net_940, net_956, net_972, 825 net_988}), .vdd(vdd), .gnd(gnd)); 826 endmodule /* memory__regfile16 */ 827 828 module lisp_coproc(addr, clk, cs, data_in, rst, rw, data_out, vdd, gnd); 829 input [2:0] addr; 830 input clk; 831 input cs; 832 input [7:0] data_in; 833 input rst; 834 input rw; 835 output [7:0] data_out; 836 input vdd; 837 input gnd; 838 839 supply1 vdd; 840 supply0 gnd; 841 wire fsm_0_alu_en, net_63, net_65, net_67, net_139, net_141, net_143, net_172; 842 wire net_204, net_207, net_214, net_219, net_221, net_223, net_227, net_228; 843 wire net_240, net_241, net_242, net_243, net_244, net_266, net_299, net_301; 844 wire net_372, net_374, net_377, net_378, net_381, net_382, net_385, net_393; 845 wire net_465, net_467, net_534, net_547, net_564, net_569, net_579, net_587; 846 wire net_591, net_634, net_645, net_646, net_652, net_653, net_654, net_668; 847 wire net_703, net_704, net_707, net_708, net_710, net_713, net_714, net_717; 848 wire net_718, net_721, net_722, net_725, net_772, net_773, net_774, net_820; 849 wire net_1043, net_1083, net_1182, net_1183, net_1184, net_1493, net_1498; 850 wire net_1502, net_1504; 851 wire [7:3] ioreg5_0_q_opcode; 852 853 memory__bumpallocator bumpallo_0(.clk(clk), .rst(rst), .inc_en(net_266), 854 .ptr({net_652, net_653, net_654, net_634}), .vdd(vdd), .gnd(gnd)); 855 datapath__eq_8bit eq_8bit_0(.a({net_708, net_707, net_704, net_703, net_774, 856 net_773, net_772, net_820}), .b({net_710, net_725, net_722, net_721, 857 net_718, net_717, net_714, net_713}), .eq(net_587), .vdd(vdd), 858 .gnd(gnd)); 859 control__fsm fsm_0(.a(addr[2:0]), .clk(clk), .cs(cs), .op({net_1184, 860 net_1183, net_1182}), .rst(rst), .rw(rw), .alu_en(fsm_0_alu_en), 861 .busy(net_1502), .heap_wen(net_1504), .q_exec_cdr(net_1493), 862 .reg_wen(net_1498), .vdd(vdd), .gnd(gnd)); 863 stdcells__inv inv_0(.x(net_1184), .y(net_301), .vdd(vdd), .gnd(gnd)); 864 stdcells__inv inv_1(.x(net_299), .y(net_266), .vdd(vdd), .gnd(gnd)); 865 memory__ioreg5 ioreg5_0(.a(addr[2:0]), .clk(clk), .data_in(data_in[7:0]), 866 .data_out(data_out[0:0]), .global_en(cs), .reg_wen(net_1498), 867 .result_in({net_172, net_207, net_204, net_240, net_241, net_242, 868 net_243, net_244}), .rst(rst), .status_busy(net_1502), 869 .status_carry(net_1043), .status_err_heap(net_668), 870 .status_err_type(net_668), .status_zero(net_587), 871 .data_out_1(data_out[7:1]), .q_arg1({net_708, net_707, net_704, net_703, 872 net_774, net_773, net_772, net_820}), .q_arg2({net_710, net_725, net_722, 873 net_721, net_718, net_717, net_714, net_713}), 874 .q_opcode({ioreg5_0_q_opcode[7], ioreg5_0_q_opcode[6], 875 ioreg5_0_q_opcode[5], ioreg5_0_q_opcode[4], ioreg5_0_q_opcode[3], 876 net_1184, net_1183, net_1182}), .gnd(gnd), .vdd(vdd)); 877 stdcells__mux2 mux2_0(.i({net_587, net_579}), .s(net_1182), .z(net_591), 878 .vdd(vdd), .gnd(gnd)); 879 datapath__mux2_8bit mux2_8bi_0(.i0({net_708, net_707, net_704, net_703, 880 net_774, net_773, net_772, net_820}), .i1({net_710, net_725, net_722, 881 net_721, net_718, net_717, net_714, net_713}), .s(net_1493), .z({net_219, 882 net_221, net_223, net_227, net_228, net_143, net_141, net_139}), 883 .vdd(vdd), .gnd(gnd)); 884 datapath__mux3_4bit mux3_4bi_0(.i0({net_774, net_773, net_772, net_820}), 885 .i1({net_652, net_653, net_654, net_634}), .i2({net_652, net_653, 886 net_654, net_634}), .s({net_1493, net_1504}), .z({net_214, net_63, 887 net_65, net_67}), .vdd(vdd), .gnd(gnd)); 888 datapath__mux4_8bit mux4_8bi_0(.i0({net_393, net_372, net_374, net_377, 889 net_378, net_381, net_382, net_385}), .i1({net_467, net_467, net_465, 890 net_465, net_652, net_653, net_654, net_634}), .i2({net_467, net_465, 891 net_534, net_547, net_646, net_645, net_564, net_569}), .i3({net_465, 892 net_591, net_465, net_465, net_465, net_465, net_465, net_591}), 893 .s({net_1184, net_1182}), .z({net_172, net_207, net_204, net_240, 894 net_241, net_242, net_243, net_244}), .vdd(vdd), .gnd(gnd)); 895 stdcells__nand2 nand2_0(.x(net_707), .y(net_708), .z(net_579), .vdd(vdd), 896 .gnd(gnd)); 897 stdcells__nand3 nand3_0(.w(net_1498), .x(net_301), .y(net_1182), .z(net_299), 898 .vdd(vdd), .gnd(gnd)); 899 datapath__rca_6bit rca_6bit_0(.a({net_704, net_703, net_774, net_773, 900 net_772, net_820}), .b({net_722, net_721, net_718, net_717, net_714, 901 net_713}), .cin(net_1083), .cout(net_1043), .s({net_534, net_547, 902 net_646, net_645, net_564, net_569}), .vdd(vdd), .gnd(gnd)); 903 memory__regfile16 regfile1_0(.clk(clk), .r_addr({net_774, net_773, net_772, 904 net_820}), .rst(rst), .w_addr({net_214, net_63, net_65, net_67}), 905 .w_data({net_219, net_221, net_223, net_227, net_228, net_143, net_141, 906 net_139}), .w_en(net_1504), .r_data({net_393, net_372, net_374, net_377, 907 net_378, net_381, net_382, net_385}), .vdd(vdd), .gnd(gnd)); 908 stdcells__tiehigh tiehigh_0(.y(net_467), .vdd(vdd), .gnd(gnd)); 909 stdcells__tielow tielow_0(.y(net_465), .vdd(vdd), .gnd(gnd)); 910 stdcells__tielow tielow_1(.y(net_668), .vdd(vdd), .gnd(gnd)); 911 stdcells__tielow tielow_2(.y(net_1083), .vdd(vdd), .gnd(gnd)); 912 endmodule /* lisp_coproc */