| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2025-12-10 | migrate from electric vlsi to librelane/sky130 flowHEADmaster | vin | 6 | -510/+631 | |
| this is quite a major shift. moves the project from a manual, full-custom layout workflow to a more modern automated flow and a more modern process (130nm vs 350nm). also improved the testbench. migration also resolves previous manual routing-caused errors (like the CONS logic bug and difficulty in implementing TG logic). this nearly halved the transistor count from 15k to 8k and reduced area size by 300x. | |||||
| 2025-12-08 | final changes from electric before moving to librelane | vin | 8 | -309/+10997 | |
| This is the commit used for my class's final report. Now I'm free to use whatever tool I want. Cadence/Synopsys seems to be much more automated compared to Electric, and LibreLane (previously OpenLane) seems to be more closely resemble that. | |||||
| 2025-12-01 | fix mux16 layout input ordering | vin | 1 | -76/+77 | |
| 2025-12-01 | some more changes | vin | 1 | -113/+1230 | |
| 2025-11-30 | add more gates and make some changes to layouts for easier tiling | vin | 3 | -410/+2158 | |
| 2025-11-29 | add 6-bit rca and 8-bit equivalent | vin | 2 | -84/+829 | |
| 2025-11-28 | finish making primitive cells (passes DRC+ERC+LVS) | vin | 1 | -0/+1189 | |
| 2025-11-20 | add more comprehensive test bench | vin | 1 | -94/+254 | |
| 2025-11-20 | fix lint errors from icarus-verilog and verilator | vin | 1 | -5/+10 | |
| 2025-11-20 | fix rtl, now tests all pass | vin | 3 | -317/+240 | |
| need to go through the sv files again and also run a linter | |||||
| 2025-11-20 | initial golden rtl | vin | 3 | -0/+442 | |
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index : cda4210_lisp_coproc | |
| A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) | Vineet K |
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