| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2025-12-10 | migrate from electric vlsi to librelane/sky130 flowHEADmaster | vin | 2 | -508/+556 |
| 2025-11-20 | add more comprehensive test bench | vin | 1 | -94/+254 |
| 2025-11-20 | fix lint errors from icarus-verilog and verilator | vin | 1 | -5/+10 |
| 2025-11-20 | fix rtl, now tests all pass | vin | 2 | -316/+238 |
| 2025-11-20 | initial golden rtl | vin | 2 | -0/+439 |
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index : cda4210_lisp_coproc | |
| A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) | Vineet K |
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