path: root/vlsi/chip_core.v

/* Verilog for cell 'chip_core{sch}' from library 'toplevel' */
/* Created on Thu Dec 04, 2025 14:22:13 */
/* Last revised on Thu Dec 04, 2025 21:10:21 */
/* Written on Thu Dec 04, 2025 21:10:31 by Electric VLSI Design System, version 9.08 */

module stdcells__inv(x, y);
   input x;
   output y;

   assign y = ~x;
endmodule   /* stdcells__inv */

module stdcells__nand2(x, y, z);
   input x;
   input y;
   output z;

   assign z = ~(x & y);
endmodule   /* stdcells__nand2 */

module stdcells__mux2(i, s, z);
   input [1:0] i;
   input       s;
   output      z;

   supply1     vdd;
   supply0     gnd;
   wire	       net_28, net_32, net_36;

   stdcells__inv inv2_4(.x(s), .y(net_36));
   stdcells__nand2 nand2_0(.x(i[1]), .y(s), .z(net_28));
   stdcells__nand2 nand2_1(.x(i[0]), .y(net_36), .z(net_32));
   stdcells__nand2 nand2_2(.x(net_28), .y(net_32), .z(z));
endmodule   /* stdcells__mux2 */

module stdcells__tielow(y);
   output y;

   assign y = 0;
endmodule   /* stdcells__tielow */

module stdcells__dff(clk, d, rst, q);
   input clk;
   input d;
   input rst;
   output reg q; // 'reg' is needed for behavioral assignment

   always @(posedge clk or posedge rst) begin
      if (rst) begin
	 q <= 1'b0; // Async Reset (Active High)
      end else begin
	 q <= d;    // Data Capture
      end
   end
endmodule

module memory__dffe(clk, d, en, rst, q);
   input clk;
   input d;
   input en;
   input rst;
   output q;

   supply1 vdd;
   supply0 gnd;
   wire	   net_5;

   stdcells__dff dff_0(.clk(clk), .d(net_5), .rst(rst), .q(q));
   stdcells__mux2 mux2_0(.i({d, q}), .s(en), .z(net_5));
endmodule   /* memory__dffe */

module stdcells__xor2(x, y, z);
   input x;
   input y;
   output z;

   supply1 vdd;
   supply0 gnd;
   wire	   net_17, net_24, net_25;

   stdcells__nand2 nand2_0(.x(x), .y(y), .z(net_17));
   stdcells__nand2 nand2_1(.x(x), .y(net_17), .z(net_24));
   stdcells__nand2 nand2_2(.x(net_24), .y(net_25), .z(z));
   stdcells__nand2 nand2_3(.x(y), .y(net_17), .z(net_25));
endmodule   /* stdcells__xor2 */

module memory__bumpallocator(clk, inc_en, rst, ptr);
   input clk;
   input inc_en;
   input rst;
   output [3:0]	ptr;

   supply1	vdd;
   supply0	gnd;
   wire		net_27, net_34, net_57, net_59, net_68;

   memory__dffe dffe_0(.clk(clk), .d(ptr[0]), .en(inc_en), .rst(rst), 
		       .q(ptr[0]));
   memory__dffe dffe_1(.clk(clk), .d(net_27), .en(inc_en), .rst(rst), 
		       .q(ptr[1]));
   memory__dffe dffe_2(.clk(clk), .d(net_34), .en(inc_en), .rst(rst), 
		       .q(ptr[2]));
   memory__dffe dffe_3(.clk(clk), .d(net_68), .en(inc_en), .rst(rst), 
		       .q(ptr[3]));
   stdcells__inv inv_2(.x(ptr[1]), .y(net_27));
   stdcells__inv inv_3(.x(net_57), .y(net_59));
   stdcells__nand2 nand2_1(.x(ptr[1]), .y(ptr[2]), .z(net_57));
   stdcells__xor2 xor2_2(.x(ptr[2]), .y(ptr[1]), .z(net_34));
   stdcells__xor2 xor2_3(.x(ptr[3]), .y(net_59), .z(net_68));
endmodule   /* memory__bumpallocator */

module stdcells__nor2(x, y, z);
   input x;
   input y;
   output z;

   assign z = ~(x | y);
endmodule   /* stdcells__nor2 */

module datapath__eq_8bit(a, b, eq);
   input [7:0] a;
   input [7:0] b;
   output      eq;

   supply1     vdd;
   supply0     gnd;
   wire	       net_4, net_5, net_6, net_7, net_8, net_9, net_10, net_12, net_14, net_16;
   wire	       net_18, net_21, net_24, net_26;

   stdcells__nand2 nand2_0(.x(net_4), .y(net_5), .z(net_24));
   stdcells__nand2 nand2_1(.x(net_6), .y(net_7), .z(net_26));
   stdcells__nor2 nor2_0(.x(net_21), .y(net_16), .z(net_4));
   stdcells__nor2 nor2_1(.x(net_14), .y(net_8), .z(net_5));
   stdcells__nor2 nor2_2(.x(net_9), .y(net_10), .z(net_6));
   stdcells__nor2 nor2_3(.x(net_12), .y(net_18), .z(net_7));
   stdcells__nor2 nor2_4(.x(net_24), .y(net_26), .z(eq));
   stdcells__xor2 xor2_1(.x(a[0]), .y(b[0]), .z(net_21));
   stdcells__xor2 xor2_2(.x(a[1]), .y(b[1]), .z(net_16));
   stdcells__xor2 xor2_3(.x(a[2]), .y(b[2]), .z(net_14));
   stdcells__xor2 xor2_4(.x(a[3]), .y(b[3]), .z(net_8));
   stdcells__xor2 xor2_5(.x(a[4]), .y(b[4]), .z(net_9));
   stdcells__xor2 xor2_6(.x(a[5]), .y(b[5]), .z(net_10));
   stdcells__xor2 xor2_7(.x(a[6]), .y(b[6]), .z(net_12));
   stdcells__xor2 xor2_8(.x(a[7]), .y(b[7]), .z(net_18));
endmodule   /* datapath__eq_8bit */

module stdcells__nand3(w, x, y, z);
   input w;
   input x;
   input y;
   output z;

   assign z = ~(w & x & y);
endmodule   /* stdcells__nand3 */

module control__fsm(a, clk, cs, op, rst, rw, alu_en, busy, heap_wen, 
		    q_exec_cdr, reg_wen);
   input [2:0] a;
   input       clk;
   input       cs;
   input [2:0] op;
   input       rst;
   input       rw;
   output      alu_en;
   output      busy;
   output      heap_wen;
   output      q_exec_cdr;
   output      reg_wen;

   supply1     vdd;
   supply0     gnd;
   wire	       _all_zeros, _stay, cons_first_half, net_24, net_26, net_31, net_33;
   wire	       net_35, net_37, net_38, net_40, net_42, net_53, net_59, net_70, net_79;
   wire	       net_108, net_134, net_142, net_144, net_161, net_172, net_228, net_229;
   wire	       q_decode, q_idle;

   stdcells__dff dff_1(.clk(clk), .d(net_108), .rst(rst), .q(q_idle));
   stdcells__dff dff_2(.clk(clk), .d(net_161), .rst(rst), .q(reg_wen));
   stdcells__dff dff_3(.clk(clk), .d(cons_first_half), .rst(rst), 
		       .q(q_exec_cdr));
   stdcells__dff dff_4(.clk(clk), .d(net_59), .rst(rst), .q(q_decode));
   stdcells__dff dff_5(.clk(clk), .d(q_decode), .rst(rst), .q(alu_en));
   stdcells__inv inv_0(.x(rw), .y(net_31));
   stdcells__inv inv_1(.x(a[0]), .y(net_35));
   stdcells__inv inv_2(.x(a[1]), .y(net_37));
   stdcells__inv inv_3(.x(a[2]), .y(net_33));
   stdcells__inv inv_5(.x(net_53), .y(net_59));
   stdcells__inv inv_6(.x(net_38), .y(net_70));
   stdcells__inv inv_7(.x(reg_wen), .y(net_79));
   stdcells__inv inv_8(.x(q_idle), .y(busy));
   stdcells__inv inv_11(.x(alu_en), .y(net_134));
   stdcells__inv inv_12(.x(q_exec_cdr), .y(net_144));
   stdcells__inv inv_13(.x(net_172), .y(heap_wen));
   stdcells__nand2 nand2_0(.x(net_35), .y(net_37), .z(net_26));
   stdcells__nand2 nand2_1(.x(net_42), .y(net_40), .z(_all_zeros));
   stdcells__nand2 nand2_2(.x(net_38), .y(q_idle), .z(net_53));
   stdcells__nand2 nand2_3(.x(net_70), .y(q_idle), .z(_stay));
   stdcells__nand2 nand2_4(.x(net_228), .y(alu_en), .z(net_142));
   stdcells__nand2 nand2_5(.x(net_142), .y(net_144), .z(net_161));
   stdcells__nand2 nand2_6(.x(op[0]), .y(net_229), .z(net_228));
   stdcells__nand3 nand3_0(.w(cs), .x(net_31), .y(net_33), .z(net_24));
   stdcells__nand3 nand3_1(.w(_stay), .x(net_79), .y(_all_zeros), .z(net_108));
   stdcells__nor2 nor2_0(.x(net_24), .y(net_26), .z(net_38));
   stdcells__nor2 nor2_1(.x(reg_wen), .y(alu_en), .z(net_42));
   stdcells__nor2 nor2_2(.x(q_decode), .y(q_idle), .z(net_40));
   stdcells__nor2 nor2_3(.x(net_134), .y(net_228), .z(cons_first_half));
   stdcells__nor2 nor2_4(.x(cons_first_half), .y(q_exec_cdr), .z(net_172));
   stdcells__nor2 nor2_5(.x(op[1]), .y(op[2]), .z(net_229));
endmodule   /* control__fsm */

module stdcells__dec2(a0, a1, en, _q0, _q1, _q2, _q3);
   input a0;
   input a1;
   input en;
   output _q0;
   output _q1;
   output _q2;
   output _q3;

   supply1 vdd;
   supply0 gnd;
   wire	   net_20, net_24;

   stdcells__inv inv_0(.x(a0), .y(net_20));
   stdcells__inv inv_1(.x(a1), .y(net_24));
   stdcells__nand3 nand3_0(.w(net_20), .x(net_24), .y(en), .z(_q0));
   stdcells__nand3 nand3_1(.w(net_20), .x(a1), .y(en), .z(_q1));
   stdcells__nand3 nand3_2(.w(a0), .x(net_24), .y(en), .z(_q2));
   stdcells__nand3 nand3_3(.w(a0), .x(a1), .y(en), .z(_q3));
endmodule   /* stdcells__dec2 */

module datapath__mux2_8bit(i0, i1, s, z);
   input [7:0] i0;
   input [7:0] i1;
   input       s;
   output [7:0]	z;

   supply1	vdd;
   supply0	gnd;
   stdcells__mux2 mux2_0(.i({i1[0], i0[0]}), .s(s), .z(z[0]));
   stdcells__mux2 mux2_1(.i({i1[1], i0[1]}), .s(s), .z(z[1]));
   stdcells__mux2 mux2_2(.i({i1[2], i0[2]}), .s(s), .z(z[2]));
   stdcells__mux2 mux2_3(.i({i1[3], i0[3]}), .s(s), .z(z[3]));
   stdcells__mux2 mux2_4(.i({i1[4], i0[4]}), .s(s), .z(z[4]));
   stdcells__mux2 mux2_5(.i({i1[5], i0[5]}), .s(s), .z(z[5]));
   stdcells__mux2 mux2_6(.i({i1[6], i0[6]}), .s(s), .z(z[6]));
   stdcells__mux2 mux2_7(.i({i1[7], i0[7]}), .s(s), .z(z[7]));
endmodule   /* datapath__mux2_8bit */

module datapath__mux4(i, s, z);
   input [3:0] i;
   input [1:0] s;
   output      z;

   supply1     vdd;
   supply0     gnd;
   wire	       net_1, net_4;

   stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_1));
   stdcells__mux2 mux2_1(.i(i[3:2]), .s(s[0]), .z(net_4));
   stdcells__mux2 mux2_2(.i({net_4, net_1}), .s(s[1]), .z(z));
endmodule   /* datapath__mux4 */

module datapath__mux4_8bit(i0, i1, i2, i3, s, z);
   input [7:0] i0;
   input [7:0] i1;
   input [7:0] i2;
   input [7:0] i3;
   input [1:0] s;
   output [7:0]	z;

   supply1	vdd;
   supply0	gnd;
   datapath__mux4 mux4_0(.i({i3[0], i2[0], i1[0], i0[0]}), .s(s[1:0]), 
			 .z(z[0]));
   datapath__mux4 mux4_1(.i({i3[1], i2[1], i1[1], i0[1]}), .s(s[1:0]), 
			 .z(z[1]));
   datapath__mux4 mux4_2(.i({i3[2], i2[2], i1[2], i0[2]}), .s(s[1:0]), 
			 .z(z[2]));
   datapath__mux4 mux4_3(.i({i3[3], i2[3], i1[3], i0[3]}), .s(s[1:0]), 
			 .z(z[3]));
   datapath__mux4 mux4_4(.i({i3[4], i2[4], i1[4], i0[4]}), .s(s[1:0]), 
			 .z(z[4]));
   datapath__mux4 mux4_5(.i({i3[5], i2[5], i1[5], i0[5]}), .s(s[1:0]), 
			 .z(z[5]));
   datapath__mux4 mux4_6(.i({i3[6], i2[6], i1[6], i0[6]}), .s(s[1:0]), 
			 .z(z[6]));
   datapath__mux4 mux4_7(.i({i3[7], i2[7], i1[7], i0[7]}), .s(s[1:0]), 
			 .z(z[7]));
endmodule   /* datapath__mux4_8bit */

module memory__reg8(clk, d, en, rst, q);
   input clk;
   input [7:0] d;
   input       en;
   input       rst;
   output [7:0]	q;

   supply1	vdd;
   supply0	gnd;
   memory__dffe dffe_2(.clk(clk), .d(d[7]), .en(en), .rst(rst), .q(q[7]));
   memory__dffe dffe_8(.clk(clk), .d(d[6]), .en(en), .rst(rst), .q(q[6]));
   memory__dffe dffe_9(.clk(clk), .d(d[5]), .en(en), .rst(rst), .q(q[5]));
   memory__dffe dffe_10(.clk(clk), .d(d[4]), .en(en), .rst(rst), .q(q[4]));
   memory__dffe dffe_11(.clk(clk), .d(d[3]), .en(en), .rst(rst), .q(q[3]));
   memory__dffe dffe_12(.clk(clk), .d(d[2]), .en(en), .rst(rst), .q(q[2]));
   memory__dffe dffe_13(.clk(clk), .d(d[1]), .en(en), .rst(rst), .q(q[1]));
   memory__dffe dffe_14(.clk(clk), .d(d[0]), .en(en), .rst(rst), .q(q[0]));
endmodule   /* memory__reg8 */

module stdcells__tiehigh(y);
   output y;

   assign y = 1;
endmodule   /* stdcells__tiehigh */

module memory__ioreg5(a, clk, data_in, global_en, reg_wen, result_in, rst, 
		      status_busy, status_carry, status_err_heap, status_err_type, status_zero, 
		      data_out, q_arg1, q_arg2, q_opcode);
   input [2:0] a;
   input       clk;
   input [7:0] data_in;
   input       global_en;
   input       reg_wen;
   input [7:0] result_in;
   input       rst;
   input       status_busy;
   input       status_carry;
   input       status_err_heap;
   input       status_err_type;
   input       status_zero;
   output [7:0]	data_out;
   output [7:0]	q_arg1;
   output [7:0]	q_arg2;
   output [7:0]	q_opcode;

   supply1	vdd;
   supply0	gnd;
   wire		net_35, net_36, net_37, net_44, net_45, net_52, net_73, net_75, net_76;
   wire		net_145, net_147, net_148, net_314, net_345, net_346, net_517, net_520;
   wire		net_523, net_526, net_529, net_532, net_535, net_617, net_619, net_621;
   wire		net_623, net_625, net_627, net_629, net_631, net_778, net_780, net_783;
   wire		net_786, net_789, net_792, net_795, net_869, net_1080, net_1328;
   wire		net_1330, net_1334, net_1338, net_1342, net_1346, net_1350, net_1354;

   stdcells__dec2 dec2_0(.a0(a[0]), .a1(a[1]), .en(net_76), ._q0(net_52), 
			 ._q1(net_314), ._q2(net_45), ._q3(net_44));
   stdcells__inv inv_2(.x(net_45), .y(net_37));
   stdcells__inv inv_3(.x(net_314), .y(net_36));
   stdcells__inv inv_4(.x(net_52), .y(net_35));
   stdcells__inv inv_5(.x(a[2]), .y(net_75));
   stdcells__inv inv_6(.x(net_73), .y(net_76));
   stdcells__inv inv_8(.x(net_147), .y(net_148));
   stdcells__inv inv_9(.x(net_44), .y(net_145));
   datapath__mux2_8bit mux2_8bi_0(.i0({net_1080, net_795, net_792, net_789, 
				       net_786, net_783, net_780, net_778}), .i1({net_617, net_619, net_621, 
										  net_623, net_625, net_627, net_629, net_631}), .s(a[2]), 
				  .z(data_out[7:0]));
   datapath__mux2_8bit mux2_8bi_1(.i0(data_in[7:0]), .i1(result_in[7:0]), 
				  .s(reg_wen), .z({net_1328, net_1330, net_1334, net_1338, net_1342, 
						   net_1346, net_1350, net_1354}));
   datapath__mux4_8bit mux4_8bi_1(.i0(q_opcode[7:0]), .i1(q_arg1[7:0]), 
				  .i2(q_arg2[7:0]), .i3({net_535, net_532, net_529, net_526, net_523, 
							 net_520, net_517, net_869}), .s(a[1:0]), .z({net_1080, net_795, net_792, 
												      net_789, net_786, net_783, net_780, net_778}));
   stdcells__nand2 nand2_0(.x(net_75), .y(global_en), .z(net_73));
   stdcells__nor2 nor2_0(.x(reg_wen), .y(net_145), .z(net_147));
   memory__reg8 reg8_0(.clk(clk), .d({net_346, net_346, net_346, status_zero, 
				      status_carry, status_err_type, status_err_heap, status_busy}), 
		       .en(net_345), .rst(rst), .q({net_617, net_619, net_621, net_623, net_625, 
						    net_627, net_629, net_631}));
   memory__reg8 reg8_1(.clk(clk), .d({net_1328, net_1330, net_1334, net_1338, 
				      net_1342, net_1346, net_1350, net_1354}), .en(net_148), .rst(rst), 
		       .q({net_535, net_532, net_529, net_526, net_523, net_520, net_517, 
			   net_869}));
   memory__reg8 reg8_2(.clk(clk), .d(data_in[7:0]), .en(net_37), .rst(rst), 
		       .q(q_arg2[7:0]));
   memory__reg8 reg8_3(.clk(clk), .d(data_in[7:0]), .en(net_36), .rst(rst), 
		       .q(q_arg1[7:0]));
   memory__reg8 reg8_4(.clk(clk), .d(data_in[7:0]), .en(net_35), .rst(rst), 
		       .q(q_opcode[7:0]));
   stdcells__tiehigh tiehigh_0(.y(net_345));
   stdcells__tielow tielow_0(.y(net_346));
endmodule   /* memory__ioreg5 */

module datapath__mux3(i, s, z);
   input [2:0] i;
   input [1:0] s;
   output      z;

   supply1     vdd;
   supply0     gnd;
   wire	       net_5;

   stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_5));
   stdcells__mux2 mux2_1(.i({i[2], net_5}), .s(s[1]), .z(z));
endmodule   /* datapath__mux3 */

module datapath__mux3_4bit(i0, i1, i2, s, z);
   input [3:0] i0;
   input [3:0] i1;
   input [3:0] i2;
   input [1:0] s;
   output [3:0]	z;

   supply1	vdd;
   supply0	gnd;
   datapath__mux3 mux3_0(.i({i2[0], i1[0], i0[0]}), .s(s[1:0]), .z(z[0]));
   datapath__mux3 mux3_1(.i({i2[1], i1[1], i0[1]}), .s(s[1:0]), .z(z[1]));
   datapath__mux3 mux3_2(.i({i2[2], i1[2], i0[2]}), .s(s[1:0]), .z(z[2]));
   datapath__mux3 mux3_3(.i({i2[3], i1[3], i0[3]}), .s(s[1:0]), .z(z[3]));
endmodule   /* datapath__mux3_4bit */

module stdcells__fa(a, b, cin, cout, s);
   input a;
   input b;
   input cin;
   output cout;
   output s;

   supply1 vdd;
   supply0 gnd;
   wire	   net_4;

   stdcells__mux2 mux2_0(.i({cin, a}), .s(net_4), .z(cout));
   stdcells__xor2 xor2_0(.x(a), .y(b), .z(net_4));
   stdcells__xor2 xor2_1(.x(net_4), .y(cin), .z(s));
endmodule   /* stdcells__fa */

module datapath__rca_6bit(a, b, cin, cout, s);
   input [5:0] a;
   input [5:0] b;
   input       cin;
   output      cout;
   output [5:0]	s;

   supply1	vdd;
   supply0	gnd;
   wire		net_2, net_3, net_4, net_5, net_10;

   stdcells__fa fa_0_(.a(a[0]), .b(b[0]), .cin(cin), .cout(net_5), .s(s[0]));
   stdcells__fa fa_1_(.a(a[1]), .b(b[1]), .cin(net_5), .cout(net_4), .s(s[1]));
   stdcells__fa fa_2_(.a(a[2]), .b(b[2]), .cin(net_4), .cout(net_3), .s(s[2]));
   stdcells__fa fa_3_(.a(a[3]), .b(b[3]), .cin(net_3), .cout(net_10), 
		      .s(s[3]));
   stdcells__fa fa_4_(.a(a[4]), .b(b[4]), .cin(net_10), .cout(net_2), 
		      .s(s[4]));
   stdcells__fa fa_5_(.a(a[5]), .b(b[5]), .cin(net_2), .cout(cout), .s(s[5]));
endmodule   /* datapath__rca_6bit */

module memory__dec4(a, en, q);
   input [3:0] a;
   input       en;
   output [15:0] q;

   supply1	 vdd;
   supply0	 gnd;
   wire		 net_5, net_17, net_20, net_23, net_62, net_76, net_88, net_89;

   stdcells__dec2 dec2_0(.a0(a[3]), .a1(a[2]), .en(en), ._q0(net_5), 
			 ._q1(net_17), ._q2(net_20), ._q3(net_23));
   stdcells__dec2 dec2_1(.a0(a[1]), .a1(a[0]), .en(en), ._q0(net_62), 
			 ._q1(net_76), ._q2(net_88), ._q3(net_89));
   stdcells__nor2 nor2_0(.x(net_5), .y(net_62), .z(q[0]));
   stdcells__nor2 nor2_1(.x(net_5), .y(net_76), .z(q[1]));
   stdcells__nor2 nor2_2(.x(net_5), .y(net_88), .z(q[2]));
   stdcells__nor2 nor2_3(.x(net_5), .y(net_89), .z(q[3]));
   stdcells__nor2 nor2_4(.x(net_17), .y(net_62), .z(q[4]));
   stdcells__nor2 nor2_5(.x(net_17), .y(net_76), .z(q[5]));
   stdcells__nor2 nor2_6(.x(net_17), .y(net_88), .z(q[6]));
   stdcells__nor2 nor2_7(.x(net_17), .y(net_89), .z(q[7]));
   stdcells__nor2 nor2_8(.x(net_20), .y(net_62), .z(q[8]));
   stdcells__nor2 nor2_9(.x(net_20), .y(net_76), .z(q[9]));
   stdcells__nor2 nor2_10(.x(net_20), .y(net_88), .z(q[10]));
   stdcells__nor2 nor2_11(.x(net_20), .y(net_89), .z(q[11]));
   stdcells__nor2 nor2_12(.x(net_23), .y(net_62), .z(q[12]));
   stdcells__nor2 nor2_13(.x(net_23), .y(net_76), .z(q[13]));
   stdcells__nor2 nor2_14(.x(net_23), .y(net_88), .z(q[14]));
   stdcells__nor2 nor2_15(.x(net_23), .y(net_89), .z(q[15]));
endmodule   /* memory__dec4 */

module memory__mux16(i, s, z);
   input [15:0] i;
   input [3:0]	s;
   output	z;

   supply1	vdd;
   supply0	gnd;
   wire		net_65, net_67, net_70, net_72, net_75, net_77, net_80, net_82, net_85;
   wire		net_87, net_88, net_90, net_95, net_97;

   stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_65));
   stdcells__mux2 mux2_1(.i({i[2], i[3]}), .s(s[0]), .z(net_67));
   stdcells__mux2 mux2_2(.i(i[5:4]), .s(s[0]), .z(net_72));
   stdcells__mux2 mux2_3(.i({i[6], i[7]}), .s(s[0]), .z(net_70));
   stdcells__mux2 mux2_4(.i(i[9:8]), .s(s[0]), .z(net_75));
   stdcells__mux2 mux2_5(.i({i[10], i[11]}), .s(s[0]), .z(net_77));
   stdcells__mux2 mux2_6(.i(i[13:12]), .s(s[0]), .z(net_80));
   stdcells__mux2 mux2_7(.i({i[14], i[15]}), .s(s[0]), .z(net_82));
   stdcells__mux2 mux2_8(.i({net_67, net_65}), .s(s[1]), .z(net_85));
   stdcells__mux2 mux2_9(.i({net_70, net_72}), .s(s[1]), .z(net_87));
   stdcells__mux2 mux2_10(.i({net_77, net_75}), .s(s[1]), .z(net_88));
   stdcells__mux2 mux2_11(.i({net_82, net_80}), .s(s[1]), .z(net_90));
   stdcells__mux2 mux2_12(.i({net_87, net_85}), .s(s[2]), .z(net_97));
   stdcells__mux2 mux2_13(.i({net_90, net_88}), .s(s[2]), .z(net_95));
   stdcells__mux2 mux2_14(.i({net_95, net_97}), .s(s[3]), .z(z));
endmodule   /* memory__mux16 */

module memory__regfile16(clk, r_addr, rst, w_addr, w_data, w_en, r_data);
   input clk;
   input [3:0] r_addr;
   input       rst;
   input [3:0] w_addr;
   input [7:0] w_data;
   input       w_en;
   output [7:0]	r_data;

   supply1	vdd;
   supply0	gnd;
   wire		net_0, net_99, net_102, net_103, net_104, net_105, net_106, net_107;
   wire		net_108, net_109, net_110, net_111, net_112, net_113, net_114, net_115;
   wire		net_413, net_414, net_415, net_416, net_417, net_418, net_419, net_420;
   wire		net_424, net_425, net_426, net_427, net_428, net_429, net_430, net_431;
   wire		net_432, net_433, net_434, net_435, net_436, net_437, net_438, net_439;
   wire		net_440, net_441, net_442, net_443, net_444, net_445, net_446, net_447;
   wire		net_448, net_449, net_450, net_451, net_452, net_453, net_454, net_455;
   wire		net_456, net_457, net_458, net_459, net_460, net_461, net_462, net_463;
   wire		net_464, net_465, net_466, net_467, net_468, net_469, net_470, net_471;
   wire		net_472, net_473, net_474, net_475, net_476, net_477, net_478, net_479;
   wire		net_480, net_481, net_482, net_483, net_484, net_485, net_486, net_487;
   wire		net_488, net_489, net_490, net_491, net_492, net_493, net_494, net_495;
   wire		net_496, net_497, net_498, net_499, net_500, net_501, net_502, net_503;
   wire		net_504, net_505, net_506, net_507, net_508, net_509, net_510, net_511;
   wire		net_512, net_513, net_514, net_515, net_516, net_517, net_518, net_519;
   wire		net_520, net_521, net_522, net_523, net_524, net_525, net_526, net_527;
   wire		net_528, net_529, net_530, net_531, net_532, net_533, net_534, net_535;
   wire		net_536, net_537, net_538, net_539, net_540, net_541, net_542, net_543;

   memory__dec4 dec4_0(.a(w_addr[3:0]), .en(w_en), .q({net_115, net_114, 
						       net_113, net_112, net_111, net_110, net_109, net_108, net_107, net_106, 
						       net_105, net_104, net_103, net_102, net_99, net_0}));
   memory__mux16 mux16_0(.i({net_413, net_431, net_439, net_447, net_455, 
			     net_463, net_471, net_479, net_487, net_495, net_503, net_511, net_519, 
			     net_527, net_535, net_543}), .s(r_addr[3:0]), .z(r_data[7]));
   memory__mux16 mux16_1(.i({net_414, net_430, net_438, net_446, net_454, 
			     net_462, net_470, net_478, net_486, net_494, net_502, net_510, net_518, 
			     net_526, net_534, net_542}), .s(r_addr[3:0]), .z(r_data[6]));
   memory__mux16 mux16_2(.i({net_415, net_429, net_437, net_445, net_453, 
			     net_461, net_469, net_477, net_485, net_493, net_501, net_509, net_517, 
			     net_525, net_533, net_541}), .s(r_addr[3:0]), .z(r_data[5]));
   memory__mux16 mux16_3(.i({net_416, net_428, net_436, net_444, net_452, 
			     net_460, net_468, net_476, net_484, net_492, net_500, net_508, net_516, 
			     net_524, net_532, net_540}), .s(r_addr[3:0]), .z(r_data[4]));
   memory__mux16 mux16_4(.i({net_417, net_427, net_435, net_443, net_451, 
			     net_459, net_467, net_475, net_483, net_491, net_499, net_507, net_515, 
			     net_523, net_531, net_539}), .s(r_addr[3:0]), .z(r_data[3]));
   memory__mux16 mux16_5(.i({net_418, net_426, net_434, net_442, net_450, 
			     net_458, net_466, net_474, net_482, net_490, net_498, net_506, net_514, 
			     net_522, net_530, net_538}), .s(r_addr[3:0]), .z(r_data[2]));
   memory__mux16 mux16_6(.i({net_419, net_425, net_433, net_441, net_449, 
			     net_457, net_465, net_473, net_481, net_489, net_497, net_505, net_513, 
			     net_521, net_529, net_537}), .s(r_addr[3:0]), .z(r_data[1]));
   memory__mux16 mux16_7(.i({net_420, net_424, net_432, net_440, net_448, 
			     net_456, net_464, net_472, net_480, net_488, net_496, net_504, net_512, 
			     net_520, net_528, net_536}), .s(r_addr[3:0]), .z(r_data[0]));
   memory__reg8 reg8_0(.clk(clk), .d(w_data[7:0]), .en(net_0), .rst(rst), 
		       .q({net_543, net_542, net_541, net_540, net_539, net_538, net_537, 
			   net_536}));
   memory__reg8 reg8_1(.clk(clk), .d(w_data[7:0]), .en(net_99), .rst(rst), 
		       .q({net_535, net_534, net_533, net_532, net_531, net_530, net_529, 
			   net_528}));
   memory__reg8 reg8_2(.clk(clk), .d(w_data[7:0]), .en(net_102), .rst(rst), 
		       .q({net_527, net_526, net_525, net_524, net_523, net_522, net_521, 
			   net_520}));
   memory__reg8 reg8_3(.clk(clk), .d(w_data[7:0]), .en(net_103), .rst(rst), 
		       .q({net_519, net_518, net_517, net_516, net_515, net_514, net_513, 
			   net_512}));
   memory__reg8 reg8_4(.clk(clk), .d(w_data[7:0]), .en(net_104), .rst(rst), 
		       .q({net_511, net_510, net_509, net_508, net_507, net_506, net_505, 
			   net_504}));
   memory__reg8 reg8_5(.clk(clk), .d(w_data[7:0]), .en(net_105), .rst(rst), 
		       .q({net_503, net_502, net_501, net_500, net_499, net_498, net_497, 
			   net_496}));
   memory__reg8 reg8_6(.clk(clk), .d(w_data[7:0]), .en(net_106), .rst(rst), 
		       .q({net_495, net_494, net_493, net_492, net_491, net_490, net_489, 
			   net_488}));
   memory__reg8 reg8_7(.clk(clk), .d(w_data[7:0]), .en(net_107), .rst(rst), 
		       .q({net_487, net_486, net_485, net_484, net_483, net_482, net_481, 
			   net_480}));
   memory__reg8 reg8_8(.clk(clk), .d(w_data[7:0]), .en(net_108), .rst(rst), 
		       .q({net_479, net_478, net_477, net_476, net_475, net_474, net_473, 
			   net_472}));
   memory__reg8 reg8_9(.clk(clk), .d(w_data[7:0]), .en(net_109), .rst(rst), 
		       .q({net_471, net_470, net_469, net_468, net_467, net_466, net_465, 
			   net_464}));
   memory__reg8 reg8_10(.clk(clk), .d(w_data[7:0]), .en(net_110), .rst(rst), 
			.q({net_463, net_462, net_461, net_460, net_459, net_458, net_457, 
			    net_456}));
   memory__reg8 reg8_11(.clk(clk), .d(w_data[7:0]), .en(net_111), .rst(rst), 
			.q({net_455, net_454, net_453, net_452, net_451, net_450, net_449, 
			    net_448}));
   memory__reg8 reg8_12(.clk(clk), .d(w_data[7:0]), .en(net_112), .rst(rst), 
			.q({net_447, net_446, net_445, net_444, net_443, net_442, net_441, 
			    net_440}));
   memory__reg8 reg8_13(.clk(clk), .d(w_data[7:0]), .en(net_113), .rst(rst), 
			.q({net_439, net_438, net_437, net_436, net_435, net_434, net_433, 
			    net_432}));
   memory__reg8 reg8_14(.clk(clk), .d(w_data[7:0]), .en(net_114), .rst(rst), 
			.q({net_431, net_430, net_429, net_428, net_427, net_426, net_425, 
			    net_424}));
   memory__reg8 reg8_15(.clk(clk), .d(w_data[7:0]), .en(net_115), .rst(rst), 
			.q({net_413, net_414, net_415, net_416, net_417, net_418, net_419, 
			    net_420}));
endmodule   /* memory__regfile16 */

module chip_core(addr, clk, cs, data_in, rst, rw, data_out);
   input [2:0] addr;
   input       clk;
   input       cs;
   input [7:0] data_in;
   input       rst;
   input       rw;
   output [7:0]	data_out;

   supply1	vdd;
   supply0	gnd;
   wire		fsm_1_alu_en, net_31, net_68, net_69, net_70, net_143, net_145, net_151;
   wire		net_155, net_159, net_162, net_165, net_207, net_242, net_259, net_260;
   wire		net_261, net_262, net_263, net_264, net_265, net_266, net_267, net_268;
   wire		net_269, net_286, net_287, net_288, net_289, net_290, net_378, net_380;
   wire		net_411, net_416, net_421, net_422, net_425, net_426, net_427, net_428;
   wire		net_429, net_430, net_431, net_474, net_475, net_476, net_477, net_504;
   wire		net_507, net_509, net_510, net_513, net_515, net_539, net_571, net_637;
   wire		net_642, net_646, net_649, net_652, net_668, net_670, net_672, net_674;
   wire		net_676, net_777, net_916, net_1054, net_1084, net_1098, net_1129;
   wire		net_1130, net_1143, net_1147, net_1165;
   wire [7:3]	ioreg5_1_q_opcode;

   memory__bumpallocator bumpallo_0(.clk(clk), .inc_en(net_1143), .rst(rst), 
				    .ptr({net_474, net_475, net_476, net_477}));
   datapath__eq_8bit eq_8bit_0(.a({net_267, net_268, net_269, net_286, net_287, 
				   net_288, net_289, net_290}), .b({net_259, net_260, net_261, net_262, 
								    net_263, net_264, net_265, net_266}), .eq(net_380));
   control__fsm fsm_1(.a(addr[2:0]), .clk(clk), .cs(cs), .op({net_70, net_69, 
							      net_68}), .rst(rst), .rw(rw), .alu_en(fsm_1_alu_en), .busy(net_421), 
		      .heap_wen(net_31), .q_exec_cdr(net_416), .reg_wen(net_207));
   stdcells__inv inv_0(.x(net_70), .y(net_1130));
   stdcells__inv inv_1(.x(net_1129), .y(net_1143));
   stdcells__inv inv_2(.x(net_1147), .y(net_539));
   stdcells__inv inv_3(.x(net_69), .y(net_1165));
   memory__ioreg5 ioreg5_1(.a(addr[2:0]), .clk(clk), .data_in(data_in[7:0]), 
			   .global_en(cs), .reg_wen(net_207), .result_in({net_165, net_162, net_159, 
									  net_242, net_155, net_151, net_145, net_143}), .rst(rst), 
			   .status_busy(net_421), .status_carry(net_504), .status_err_heap(net_378), 
			   .status_err_type(net_378), .status_zero(net_380), 
			   .data_out(data_out[7:0]), .q_arg1({net_267, net_268, net_269, net_286, 
							      net_287, net_288, net_289, net_290}), .q_arg2({net_259, net_260, net_261, 
													     net_262, net_263, net_264, net_265, net_266}), 
			   .q_opcode({ioreg5_1_q_opcode[7], ioreg5_1_q_opcode[6], 
				      ioreg5_1_q_opcode[5], ioreg5_1_q_opcode[4], ioreg5_1_q_opcode[3], net_70, 
				      net_69, net_68}));
   stdcells__mux2 mux2_0(.i({net_380, net_571}), .s(net_68), .z(net_1084));
   datapath__mux2_8bit mux2_8bi_0(.i0({net_267, net_268, net_269, net_286, 
				       net_287, net_288, net_289, net_290}), .i1({net_259, net_260, net_261, 
										  net_262, net_263, net_264, net_265, net_266}), .s(net_416), .z({net_676, 
																		  net_674, net_672, net_670, net_668, net_652, net_649, net_646}));
   datapath__mux3_4bit mux3_4bi_0(.i0({net_287, net_288, net_289, net_290}), 
				  .i1({net_474, net_475, net_476, net_477}), .i2({net_474, net_475, 
										  net_476, net_477}), .s({net_416, net_31}), .z({net_411, net_642, net_777, 
																 net_637}));
   datapath__mux4_8bit mux4_8bi_0(.i0({net_431, net_430, net_429, net_428, 
				       net_427, net_426, net_425, net_422}), .i1({net_1054, net_1054, net_916, 
										  net_916, net_474, net_475, net_476, net_477}), .i2({net_1054, net_916, 
																      net_515, net_513, net_510, net_509, net_507, net_1098}), .i3({net_916, 
																								    net_1084, net_916, net_916, net_916, net_916, net_916, net_1084}), 
				  .s({net_70, net_539}), .z({net_165, net_162, net_159, net_242, net_155, 
							     net_151, net_145, net_143}));
   stdcells__nand2 nand2_0(.x(net_268), .y(net_267), .z(net_571));
   stdcells__nand2 nand2_1(.x(net_68), .y(net_1165), .z(net_1147));
   stdcells__nand3 nand3_0(.w(net_207), .x(net_1130), .y(net_68), 
			   .z(net_1129));
   datapath__rca_6bit rca_6bit_0(.a({net_269, net_286, net_287, net_288, 
				     net_289, net_290}), .b({net_261, net_262, net_263, net_264, net_265, 
							     net_266}), .cin(net_916), .cout(net_504), .s({net_515, net_513, net_510, 
													   net_509, net_507, net_1098}));
   memory__regfile16 regfile1_1(.clk(clk), .r_addr({net_287, net_288, net_289, 
						    net_290}), .rst(rst), .w_addr({net_411, net_642, net_777, net_637}), 
				.w_data({net_676, net_674, net_672, net_670, net_668, net_652, net_649, 
					 net_646}), .w_en(net_31), .r_data({net_431, net_430, net_429, net_428, 
									    net_427, net_426, net_425, net_422}));
   stdcells__tiehigh tiehigh_0(.y(net_1054));
   stdcells__tielow tielow_3(.y(net_916));
   stdcells__tielow tielow_4(.y(net_378));
endmodule   /* chip_core */