path: root/vlsi/lisp_coproc.v

/* Verilog for cell 'lisp_coproc{lay}' from library 'toplevel' */
/* Created on Thu Dec 04, 2025 22:57:37 */
/* Last revised on Sun Dec 07, 2025 22:49:44 */
/* Written on Mon Dec 08, 2025 19:06:50 by Electric VLSI Design System, version 9.08 */

module stdcells__inv(x, y, vdd, gnd);
  input x;
  output y;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire plnode_0_well, plnode_1_well;

  tranif1 nmos_1(gnd, y, x);
  tranif0 pmos_0(y, vdd, x);
endmodule   /* stdcells__inv */

module stdcells__nand2(x, y, z, vdd, gnd);
  input x;
  input y;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_262, plnode_0_well, plnode_1_well;

  tranif1 nmos_1(z, net_262, x);
  tranif1 nmos_2(net_262, gnd, y);
  tranif0 pmos_1(vdd, z, y);
  tranif0 pmos_2(z, vdd, x);
endmodule   /* stdcells__nand2 */

module stdcells__mux2(i, s, z, vdd, gnd);
  input [1:0] i;
  input s;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_6, net_8, net_12;

  stdcells__inv inv2_0(.x(s), .y(net_12), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_0(.x(i[1]), .y(s), .z(net_8), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_1(.x(i[0]), .y(net_12), .z(net_6), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_2(.x(net_8), .y(net_6), .z(z), .vdd(vdd), .gnd(gnd));
endmodule   /* stdcells__mux2 */

module stdcells__tielow(y, vdd, gnd);
  output y;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_299, plnode_0_well, plnode_1_well;

  tranif1 nmos_0(y, gnd, net_299);
  tranif0 pmos_1(vdd, net_299);
endmodule   /* stdcells__tielow */

module stdcells__dff(clk, d, rst, q, vdd, gnd);
  input clk;
  input d;
  input rst;
  output q;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_70, net_71, net_74, net_81, net_83, net_97, net_103;

  stdcells__inv inv_0(.x(clk), .y(net_97), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_1(.x(net_97), .y(net_103), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_2(.x(net_71), .y(net_70), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_3(.x(net_70), .y(q), .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_3(.i({net_74, d}), .s(rst), .z(net_81), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_4(.i({net_81, net_83}), .s(net_97), .z(net_83), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_5(.i({net_83, net_71}), .s(net_103), .z(net_71), 
      .vdd(vdd), .gnd(gnd));
  stdcells__tielow tielow_1(.y(net_74), .vdd(vdd), .gnd(gnd));
endmodule   /* stdcells__dff */

module memory__dffe(clk, d, en, rst, q, vdd, gnd);
  input clk;
  input d;
  input en;
  input rst;
  output q;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_67;

  stdcells__dff dff_2(.clk(clk), .d(net_67), .rst(rst), .q(q), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_2(.i({d, q}), .s(en), .z(net_67), .vdd(vdd), .gnd(gnd));
endmodule   /* memory__dffe */

module stdcells__xor2(x, y, z, vdd, gnd);
  input x;
  input y;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_355, net_358, net_371;

  stdcells__nand2 n1(.x(x), .y(y), .z(net_355), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 n2(.x(x), .y(net_355), .z(net_371), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 n3(.x(y), .y(net_355), .z(net_358), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 n4(.x(net_371), .y(net_358), .z(z), .vdd(vdd), .gnd(gnd));
endmodule   /* stdcells__xor2 */

module memory__bumpallocator(clk, rst, inc_en, ptr, vdd, gnd);
  input clk;
  input rst;
  output inc_en;
  output [3:0] ptr;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_12, net_33, net_35, net_37, net_63;

  memory__dffe dffe_4(.clk(clk), .d(ptr[0]), .en(inc_en), .rst(rst), 
      .q(ptr[0]), .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_5(.clk(clk), .d(net_12), .en(inc_en), .rst(rst), 
      .q(ptr[1]), .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_6(.clk(clk), .d(net_63), .en(inc_en), .rst(rst), 
      .q(ptr[2]), .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_7(.clk(clk), .d(net_37), .en(inc_en), .rst(rst), 
      .q(ptr[3]), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_0(.x(ptr[1]), .y(net_12), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_1(.x(net_33), .y(net_35), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_0(.x(ptr[1]), .y(ptr[2]), .z(net_33), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_0(.x(ptr[2]), .y(ptr[1]), .z(net_63), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_1(.x(ptr[3]), .y(net_35), .z(net_37), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* memory__bumpallocator */

module stdcells__nor2(x, y, z, vdd, gnd);
  input x;
  input y;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_322, plnode_0_well, plnode_1_well;

  tranif1 nmos_1(gnd, z, y);
  tranif1 nmos_2(z, gnd, x);
  tranif0 pmos_1(vdd, net_322, x);
  tranif0 pmos_2(net_322, z, y);
endmodule   /* stdcells__nor2 */

module datapath__eq_8bit(a, b, eq, vdd, gnd);
  input [7:0] a;
  input [7:0] b;
  output eq;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_28, net_30, net_36, net_53, net_57, net_59, net_66, net_70, net_93;
  wire net_101, net_106, net_116, net_123, net_126;

  stdcells__nand2 nand2_0(.x(net_70), .y(net_106), .z(net_30), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_1(.x(net_36), .y(net_101), .z(net_28), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_0(.x(net_123), .y(net_126), .z(net_70), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_1(.x(net_116), .y(net_93), .z(net_106), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_2(.x(net_66), .y(net_59), .z(net_36), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_3(.x(net_57), .y(net_53), .z(net_101), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_4(.x(net_30), .y(net_28), .z(eq), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_0(.x(a[0]), .y(b[0]), .z(net_123), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_1(.x(a[1]), .y(b[1]), .z(net_126), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_2(.x(a[2]), .y(b[2]), .z(net_116), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_3(.x(a[3]), .y(b[3]), .z(net_93), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_4(.x(a[4]), .y(b[4]), .z(net_66), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_5(.x(a[5]), .y(b[5]), .z(net_59), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_6(.x(a[6]), .y(b[6]), .z(net_57), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_7(.x(a[7]), .y(b[7]), .z(net_53), .vdd(vdd), .gnd(gnd));
endmodule   /* datapath__eq_8bit */

module stdcells__nand3(w, x, y, z, vdd, gnd);
  input w;
  input x;
  input y;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_262, net_316, plnode_0_well, plnode_1_well;

  tranif1 nmos_1(net_316, net_262, x);
  tranif1 nmos_2(net_262, gnd, y);
  tranif1 nmos_3(z, net_316, w);
  tranif0 pmos_1(vdd, z, y);
  tranif0 pmos_2(z, vdd, x);
  tranif0 pmos_4(vdd, z, w);
endmodule   /* stdcells__nand3 */

module control__fsm(a, clk, cs, op, rst, rw, alu_en, busy, heap_wen, 
      q_exec_cdr, reg_wen, vdd, gnd);
  input [2:0] a;
  input clk;
  input cs;
  input [2:0] op;
  input rst;
  input rw;
  output alu_en;
  output busy;
  output heap_wen;
  output q_exec_cdr;
  output reg_wen;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_26, net_40, net_43, net_73, net_77, net_88, net_99, net_114, net_116;
  wire net_128, net_132, net_147, net_159, net_167, net_190, net_200, net_202;
  wire net_206, net_223, net_225, net_228, net_236, net_397, net_422, net_425;
  wire net_435;

  stdcells__dff dff_0(.clk(clk), .d(net_159), .rst(rst), .q(net_114), 
      .vdd(vdd), .gnd(gnd));
  stdcells__dff dff_1(.clk(clk), .d(net_128), .rst(rst), .q(net_26), .vdd(vdd), 
      .gnd(gnd));
  stdcells__dff dff_2(.clk(clk), .d(net_26), .rst(rst), .q(alu_en), .vdd(vdd), 
      .gnd(gnd));
  stdcells__dff dff_3(.clk(clk), .d(net_206), .rst(rst), .q(q_exec_cdr), 
      .vdd(vdd), .gnd(gnd));
  stdcells__dff dff_4(.clk(clk), .d(net_228), .rst(rst), .q(reg_wen), 
      .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_0(.x(rw), .y(net_99), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_1(.x(a[0]), .y(net_88), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_2(.x(a[1]), .y(net_73), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_3(.x(a[2]), .y(net_77), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_4(.x(net_397), .y(net_128), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_5(.x(net_116), .y(net_132), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_6(.x(reg_wen), .y(net_147), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_7(.x(alu_en), .y(net_200), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_8(.x(q_exec_cdr), .y(net_223), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_9(.x(net_236), .y(heap_wen), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_10(.x(net_114), .y(busy), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_3(.x(net_88), .y(net_73), .z(net_43), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_4(.x(net_116), .y(net_114), .z(net_397), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_5(.x(net_132), .y(net_114), .z(net_435), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_6(.x(net_425), .y(net_422), .z(net_167), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_7(.x(op[0]), .y(net_190), .z(net_202), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_8(.x(net_202), .y(alu_en), .z(net_225), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand2 nand2_9(.x(net_225), .y(net_223), .z(net_228), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand3 nand3_0(.w(cs), .x(net_99), .y(net_77), .z(net_40), 
      .vdd(vdd), .gnd(gnd));
  stdcells__nand3 nand3_1(.w(net_435), .x(net_147), .y(net_167), .z(net_159), 
      .vdd(vdd), .gnd(gnd));
  stdcells__nor2 nor2_0(.x(reg_wen), .y(alu_en), .z(net_425), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_1(.x(net_26), .y(net_114), .z(net_422), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_2(.x(op[1]), .y(op[2]), .z(net_190), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_3(.x(net_200), .y(net_202), .z(net_206), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_4(.x(net_206), .y(q_exec_cdr), .z(net_236), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_5(.x(net_40), .y(net_43), .z(net_116), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* control__fsm */

module stdcells__dec2(a0, a1, en, _q0, _q1, _q2, _q3, vdd, gnd);
  input a0;
  input a1;
  input en;
  output _q0;
  output _q1;
  output _q2;
  output _q3;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_88, net_92;

  stdcells__inv inv_1(.x(a0), .y(net_88), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_2(.x(a1), .y(net_92), .vdd(vdd), .gnd(gnd));
  stdcells__nand3 nand3_0(.w(net_88), .x(net_92), .y(en), .z(_q0), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand3 nand3_1(.w(net_88), .x(a1), .y(en), .z(_q1), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand3 nand3_2(.w(a0), .x(net_92), .y(en), .z(_q2), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand3 nand3_3(.w(a0), .x(a1), .y(en), .z(_q3), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* stdcells__dec2 */

module datapath__mux2_8bit(i0, i1, s, z, vdd, gnd);
  input [7:0] i0;
  input [7:0] i1;
  input s;
  input [7:0] z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  stdcells__mux2 mux2_0_(.i({i1[0], i0[0]}), .s(s), .z(z[0]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_1_(.i({i1[1], i0[1]}), .s(s), .z(z[1]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_2_(.i({i1[2], i0[2]}), .s(s), .z(z[2]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_3_(.i({i1[3], i0[3]}), .s(s), .z(z[3]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_4_(.i({i1[4], i0[4]}), .s(s), .z(z[4]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_5_(.i({i1[5], i0[5]}), .s(s), .z(z[5]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_6_(.i({i1[6], i0[6]}), .s(s), .z(z[6]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_7_(.i({i1[7], i0[7]}), .s(s), .z(z[7]), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* datapath__mux2_8bit */

module datapath__mux4(i, s, z, vdd, gnd);
  input [3:0] i;
  input [1:0] s;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_4, net_7;

  stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_7), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_1(.i(i[3:2]), .s(s[0]), .z(net_4), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_2(.i({net_4, net_7}), .s(s[1]), .z(z), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* datapath__mux4 */

module datapath__mux4_8bit(i0, i1, i2, i3, s, z, vdd, gnd);
  input [7:0] i0;
  input [7:0] i1;
  input [7:0] i2;
  input [7:0] i3;
  input [1:0] s;
  output [7:0] z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  datapath__mux4 mux4_0(.i({i3[7], i2[7], i1[7], i0[7]}), .s(s[1:0]), .z(z[7]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_1(.i({i3[6], i2[6], i1[6], i0[6]}), .s(s[1:0]), .z(z[6]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_2(.i({i3[5], i2[5], i1[5], i0[5]}), .s(s[1:0]), .z(z[5]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_3(.i({i3[4], i2[4], i1[4], i0[4]}), .s(s[1:0]), .z(z[4]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_4(.i({i3[3], i2[3], i1[3], i0[3]}), .s(s[1:0]), .z(z[3]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_5(.i({i3[2], i2[2], i1[2], i0[2]}), .s(s[1:0]), .z(z[2]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_6(.i({i3[1], i2[1], i1[1], i0[1]}), .s(s[1:0]), .z(z[1]), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux4 mux4_7(.i({i3[0], i2[0], i1[0], i0[0]}), .s(s[1:0]), .z(z[0]), 
      .vdd(vdd), .gnd(gnd));
endmodule   /* datapath__mux4_8bit */

module memory__reg8(clk, d, en, rst, q, vdd, gnd);
  input clk;
  input [7:0] d;
  input en;
  input rst;
  output [7:0] q;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  memory__dffe dffe_8(.clk(clk), .d(d[7]), .en(en), .rst(rst), .q(q[7]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_9(.clk(clk), .d(d[6]), .en(en), .rst(rst), .q(q[6]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_10(.clk(clk), .d(d[5]), .en(en), .rst(rst), .q(q[5]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_11(.clk(clk), .d(d[4]), .en(en), .rst(rst), .q(q[4]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_12(.clk(clk), .d(d[3]), .en(en), .rst(rst), .q(q[3]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_13(.clk(clk), .d(d[2]), .en(en), .rst(rst), .q(q[2]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_14(.clk(clk), .d(d[1]), .en(en), .rst(rst), .q(q[1]), 
      .vdd(vdd), .gnd(gnd));
  memory__dffe dffe_15(.clk(clk), .d(d[0]), .en(en), .rst(rst), .q(q[0]), 
      .vdd(vdd), .gnd(gnd));
endmodule   /* memory__reg8 */

module stdcells__tiehigh(y, vdd, gnd);
  output y;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_299, plnode_0_well, plnode_1_well;

  tranif1 nmos_0(gnd, net_299);
  tranif0 pmos_1(vdd, y, net_299);
endmodule   /* stdcells__tiehigh */

module memory__ioreg5(a, clk, data_in, data_out, global_en, reg_wen, result_in, 
      rst, status_busy, status_carry, status_err_heap, status_err_type, 
      status_zero, data_out_1, q_arg1, q_arg2, q_opcode, gnd, vdd);
  input [2:0] a;
  input clk;
  input [7:0] data_in;
  input [0:0] data_out;
  input global_en;
  input reg_wen;
  input [7:0] result_in;
  input rst;
  input status_busy;
  input status_carry;
  input status_err_heap;
  input status_err_type;
  input status_zero;
  output [7:1] data_out_1;
  output [7:0] q_arg1;
  output [7:0] q_arg2;
  output [7:0] q_opcode;
  input gnd;
  input vdd;

  supply1 vdd;
  wire net_2, net_8, net_12, net_18, net_50, net_51, net_53, net_55, net_57;
  wire net_61, net_63, net_67, net_87, net_90, net_96, net_98, net_100, net_102;
  wire net_194, net_195, net_196, net_197, net_198, net_199, net_200, net_473;
  wire net_476, net_477, net_481, net_487, net_527, net_534, net_543, net_551;
  wire net_555, net_556, net_557, net_558, net_559, net_560, net_561, net_562;
  wire net_791, net_797, net_826, net_828, net_832;

  stdcells__dec2 dec2_0(.a0(a[0]), .a1(a[1]), .en(net_826), ._q0(net_96), 
      ._q1(net_98), ._q2(net_100), ._q3(net_102), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_0(.x(net_90), .y(net_18), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_1(.x(net_100), .y(net_12), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_2(.x(net_98), .y(net_8), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_3(.x(net_96), .y(net_2), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_4(.x(net_102), .y(net_87), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_5(.x(a[2]), .y(net_832), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_6(.x(net_828), .y(net_826), .vdd(vdd), .gnd(gnd));
  datapath__mux2_8bit mux2_8bi_0(.i0(data_in[7:0]), .i1(result_in[7:0]), 
      .s(reg_wen), .z({net_63, net_67, net_61, net_57, net_55, net_53, net_51, 
      net_50}), .vdd(vdd), .gnd(gnd));
  datapath__mux2_8bit mux2_8bi_1(.i0({net_473, net_477, net_476, net_551, 
      net_543, net_534, net_487, net_481}), .i1({net_555, net_556, net_557, 
      net_558, net_559, net_560, net_561, net_562}), .s(a[2]), 
      .z({data_out_1[7], data_out_1[6], data_out_1[5], data_out_1[4], 
      data_out_1[3], data_out_1[2], data_out_1[1], data_out[0]}), .vdd(vdd), 
      .gnd(gnd));
  datapath__mux4_8bit mux4_8bi_0(.i0(q_opcode[7:0]), .i1(q_arg1[7:0]), 
      .i2(q_arg2[7:0]), .i3({net_200, net_199, net_198, net_197, net_196, 
      net_195, net_194, net_527}), .s(a[1:0]), .z({net_473, net_477, net_476, 
      net_551, net_543, net_534, net_487, net_481}), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_0(.x(net_832), .y(global_en), .z(net_828), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_0(.x(reg_wen), .y(net_87), .z(net_90), .vdd(vdd), 
      .gnd(gnd));
  memory__reg8 reg8_0(.clk(clk), .d({net_791, net_791, net_791, status_zero, 
      status_carry, status_err_type, status_err_heap, status_busy}), 
      .en(net_797), .rst(rst), .q({net_555, net_556, net_557, net_558, net_559, 
      net_560, net_561, net_562}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_1(.clk(clk), .d({net_63, net_67, net_61, net_57, net_55, 
      net_53, net_51, net_50}), .en(net_18), .rst(rst), .q({net_200, net_199, 
      net_198, net_197, net_196, net_195, net_194, net_527}), .vdd(vdd), 
      .gnd(gnd));
  memory__reg8 reg8_2(.clk(clk), .d(data_in[7:0]), .en(net_12), .rst(rst), 
      .q(q_arg2[7:0]), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_3(.clk(clk), .d(data_in[7:0]), .en(net_8), .rst(rst), 
      .q(q_arg1[7:0]), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_4(.clk(clk), .d(data_in[7:0]), .en(net_2), .rst(rst), 
      .q(q_opcode[7:0]), .vdd(vdd), .gnd(gnd));
  stdcells__tiehigh tiehigh_0(.y(net_797), .vdd(vdd), .gnd(gnd));
  stdcells__tielow tielow_0(.y(net_791), .vdd(vdd), .gnd(gnd));
endmodule   /* memory__ioreg5 */

module datapath__mux3(i, s, z, vdd, gnd, i_1);
  input [1:0] i;
  input [1:0] s;
  output z;
  input vdd;
  input gnd;
  input [2:2] i_1;

  supply1 vdd;
  supply0 gnd;
  wire net_2;

  stdcells__mux2 mux2_0(.i(i[1:0]), .s(s[0]), .z(net_2), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_1(.i({i_1[2], net_2}), .s(s[1]), .z(z), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* datapath__mux3 */

module datapath__mux3_4bit(i0, i1, i2, s, z, vdd, gnd);
  input [3:0] i0;
  input [3:0] i1;
  input [3:0] i2;
  input [1:0] s;
  output [3:0] z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  datapath__mux3 mux3_0(.i({i1[3], i0[3]}), .s(s[1:0]), .z(z[3]), .vdd(vdd), 
      .gnd(gnd), .i_1(i2[3:3]));
  datapath__mux3 mux3_1(.i({i1[2], i0[2]}), .s(s[1:0]), .z(z[2]), .vdd(vdd), 
      .gnd(gnd), .i_1(i2[2:2]));
  datapath__mux3 mux3_2(.i({i1[1], i0[1]}), .s(s[1:0]), .z(z[1]), .vdd(vdd), 
      .gnd(gnd), .i_1(i2[1:1]));
  datapath__mux3 mux3_3(.i({i1[0], i0[0]}), .s(s[1:0]), .z(z[0]), .vdd(vdd), 
      .gnd(gnd), .i_1(i2[0:0]));
endmodule   /* datapath__mux3_4bit */

module stdcells__fa(a, b, cin, cout, s, vdd, gnd);
  input a;
  input b;
  input cin;
  output cout;
  output s;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_10;

  stdcells__mux2 mux2_1(.i({cin, a}), .s(net_10), .z(cout), .vdd(vdd), 
      .gnd(gnd));
  stdcells__xor2 xor2_0(.x(a), .y(b), .z(net_10), .vdd(vdd), .gnd(gnd));
  stdcells__xor2 xor2_1(.x(net_10), .y(cin), .z(s), .vdd(vdd), .gnd(gnd));
endmodule   /* stdcells__fa */

module datapath__rca_6bit(a, b, cin, cout, s, vdd, gnd);
  input [5:0] a;
  input [5:0] b;
  input cin;
  output cout;
  output [5:0] s;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_147, net_148, net_149, net_150, net_151;

  stdcells__fa fa_14(.a(a[0]), .b(b[0]), .cin(cin), .cout(net_148), .s(s[0]), 
      .vdd(vdd), .gnd(gnd));
  stdcells__fa fa_15(.a(a[1]), .b(b[1]), .cin(net_148), .cout(net_147), 
      .s(s[1]), .vdd(vdd), .gnd(gnd));
  stdcells__fa fa_16(.a(a[2]), .b(b[2]), .cin(net_147), .cout(net_149), 
      .s(s[2]), .vdd(vdd), .gnd(gnd));
  stdcells__fa fa_17(.a(a[3]), .b(b[3]), .cin(net_149), .cout(net_150), 
      .s(s[3]), .vdd(vdd), .gnd(gnd));
  stdcells__fa fa_18(.a(a[4]), .b(b[4]), .cin(net_150), .cout(net_151), 
      .s(s[4]), .vdd(vdd), .gnd(gnd));
  stdcells__fa fa_19(.a(a[5]), .b(b[5]), .cin(net_151), .cout(cout), .s(s[5]), 
      .vdd(vdd), .gnd(gnd));
endmodule   /* datapath__rca_6bit */

module memory__dec4(a, en, q, vdd, gnd);
  input [3:0] a;
  input en;
  output [15:0] q;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_55, net_61, net_73, net_81, net_89, net_96, net_100, net_104;

  stdcells__dec2 dec2_1(.a0(a[3]), .a1(a[2]), .en(en), ._q0(net_96), 
      ._q1(net_100), ._q2(net_104), ._q3(net_89), .vdd(vdd), .gnd(gnd));
  stdcells__dec2 dec2_2(.a0(a[1]), .a1(a[0]), .en(en), ._q0(net_55), 
      ._q1(net_61), ._q2(net_81), ._q3(net_73), .vdd(vdd), .gnd(gnd));
  stdcells__nor2 nor2_8(.x(net_96), .y(net_55), .z(q[0]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_9(.x(net_96), .y(net_61), .z(q[1]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_10(.x(net_96), .y(net_81), .z(q[2]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_11(.x(net_96), .y(net_73), .z(q[3]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_12(.x(net_100), .y(net_55), .z(q[4]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_13(.x(net_100), .y(net_61), .z(q[5]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_14(.x(net_100), .y(net_81), .z(q[6]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_15(.x(net_100), .y(net_73), .z(q[7]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_16(.x(net_104), .y(net_55), .z(q[8]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_17(.x(net_104), .y(net_61), .z(q[9]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_18(.x(net_104), .y(net_81), .z(q[10]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_19(.x(net_104), .y(net_73), .z(q[11]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_20(.x(net_89), .y(net_55), .z(q[12]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_21(.x(net_89), .y(net_61), .z(q[13]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_22(.x(net_89), .y(net_81), .z(q[14]), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nor2 nor2_23(.x(net_89), .y(net_73), .z(q[15]), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* memory__dec4 */

module memory__mux16(i, s, z, vdd, gnd);
  input [15:0] i;
  input [3:0] s;
  output z;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_174, net_176, net_179, net_182, net_184, net_186, net_188, net_190;
  wire net_193, net_195, net_199, net_201, net_204, net_206;

  stdcells__mux2 mux2_0(.i({i[14], i[15]}), .s(s[0]), .z(net_201), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_2(.i(i[13:12]), .s(s[0]), .z(net_199), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_3(.i({i[10], i[11]}), .s(s[0]), .z(net_195), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_4(.i(i[9:8]), .s(s[0]), .z(net_193), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_5(.i({i[6], i[7]}), .s(s[0]), .z(net_204), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_6(.i(i[5:4]), .s(s[0]), .z(net_206), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_7(.i({i[2], i[3]}), .s(s[0]), .z(net_190), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_8(.i(i[1:0]), .s(s[0]), .z(net_188), .vdd(vdd), 
      .gnd(gnd));
  stdcells__mux2 mux2_9(.i({net_201, net_199}), .s(s[1]), .z(net_186), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_10(.i({net_195, net_193}), .s(s[1]), .z(net_184), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_11(.i({net_204, net_206}), .s(s[1]), .z(net_182), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_12(.i({net_190, net_188}), .s(s[1]), .z(net_179), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_15(.i({net_182, net_179}), .s(s[2]), .z(net_174), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_16(.i({net_186, net_184}), .s(s[2]), .z(net_176), 
      .vdd(vdd), .gnd(gnd));
  stdcells__mux2 mux2_17(.i({net_176, net_174}), .s(s[3]), .z(z), .vdd(vdd), 
      .gnd(gnd));
endmodule   /* memory__mux16 */

module memory__regfile16(clk, r_addr, rst, w_addr, w_data, w_en, r_data, vdd, 
      gnd);
  input clk;
  input [3:0] r_addr;
  input rst;
  input [3:0] w_addr;
  input [7:0] w_data;
  input w_en;
  output [7:0] r_data;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire net_718, net_720, net_723, net_725, net_731, net_732, net_733, net_734;
  wire net_750, net_751, net_754, net_756, net_758, net_760, net_765, net_778;
  wire net_812, net_814, net_818, net_819, net_820, net_821, net_822, net_823;
  wire net_824, net_825, net_826, net_827, net_828, net_829, net_830, net_831;
  wire net_860, net_861, net_862, net_863, net_864, net_865, net_866, net_867;
  wire net_868, net_869, net_870, net_871, net_872, net_873, net_874, net_875;
  wire net_908, net_909, net_910, net_911, net_912, net_914, net_915, net_916;
  wire net_917, net_918, net_919, net_920, net_921, net_922, net_923, net_924;
  wire net_925, net_926, net_927, net_928, net_929, net_930, net_931, net_932;
  wire net_933, net_934, net_935, net_936, net_937, net_938, net_939, net_940;
  wire net_941, net_942, net_943, net_944, net_945, net_946, net_947, net_948;
  wire net_949, net_950, net_951, net_952, net_953, net_954, net_955, net_956;
  wire net_957, net_958, net_959, net_960, net_961, net_962, net_963, net_964;
  wire net_965, net_966, net_967, net_968, net_969, net_970, net_971, net_972;
  wire net_973, net_974, net_975, net_976, net_977, net_978, net_979, net_980;
  wire net_981, net_982, net_983, net_984, net_985, net_986, net_987, net_988;
  wire net_989, net_990, net_991, net_992, net_993, net_994, net_995, net_996;
  wire net_997, net_998, net_999, net_1000, net_1001, net_1002, net_1003;
  wire net_1916;

  memory__dec4 dec4_0(.a(w_addr[3:0]), .en(w_en), .q({net_750, net_751, 
      net_754, net_756, net_758, net_760, net_765, net_778, net_734, net_733, 
      net_732, net_731, net_725, net_723, net_720, net_718}), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_0(.i({net_875, net_874, net_873, net_872, net_871, 
      net_870, net_869, net_868, net_867, net_866, net_865, net_864, net_863, 
      net_862, net_861, net_860}), .s(r_addr[3:0]), .z(r_data[7]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_1(.i({net_831, net_830, net_829, net_828, net_827, 
      net_826, net_825, net_824, net_823, net_822, net_821, net_820, net_819, 
      net_818, net_814, net_812}), .s(r_addr[3:0]), .z(r_data[6]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_2(.i({net_923, net_922, net_921, net_920, net_919, 
      net_918, net_917, net_916, net_915, net_914, net_1916, net_912, net_911, 
      net_910, net_909, net_908}), .s(r_addr[3:0]), .z(r_data[5]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_3(.i({net_939, net_938, net_937, net_936, net_935, 
      net_934, net_933, net_932, net_931, net_930, net_929, net_928, net_927, 
      net_926, net_925, net_924}), .s(r_addr[3:0]), .z(r_data[4]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_4(.i({net_955, net_954, net_953, net_952, net_951, 
      net_950, net_949, net_948, net_947, net_946, net_945, net_944, net_943, 
      net_942, net_941, net_940}), .s(r_addr[3:0]), .z(r_data[3]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_5(.i({net_971, net_970, net_969, net_968, net_967, 
      net_966, net_965, net_964, net_963, net_962, net_961, net_960, net_959, 
      net_958, net_957, net_956}), .s(r_addr[3:0]), .z(r_data[2]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_6(.i({net_987, net_986, net_985, net_984, net_983, 
      net_982, net_981, net_980, net_979, net_978, net_977, net_976, net_975, 
      net_974, net_973, net_972}), .s(r_addr[3:0]), .z(r_data[1]), .vdd(vdd), 
      .gnd(gnd));
  memory__mux16 mux16_7(.i({net_1003, net_1002, net_1001, net_1000, net_999, 
      net_998, net_997, net_996, net_995, net_994, net_993, net_992, net_991, 
      net_990, net_989, net_988}), .s(r_addr[3:0]), .z(r_data[0]), .vdd(vdd), 
      .gnd(gnd));
  memory__reg8 reg8_0(.clk(clk), .d(w_data[7:0]), .en(net_750), .rst(rst), 
      .q({net_875, net_831, net_923, net_939, net_955, net_971, net_987, 
      net_1003}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_1(.clk(clk), .d(w_data[7:0]), .en(net_751), .rst(rst), 
      .q({net_874, net_830, net_922, net_938, net_954, net_970, net_986, 
      net_1002}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_2(.clk(clk), .d(w_data[7:0]), .en(net_754), .rst(rst), 
      .q({net_873, net_829, net_921, net_937, net_953, net_969, net_985, 
      net_1001}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_3(.clk(clk), .d(w_data[7:0]), .en(net_756), .rst(rst), 
      .q({net_872, net_828, net_920, net_936, net_952, net_968, net_984, 
      net_1000}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_4(.clk(clk), .d(w_data[7:0]), .en(net_758), .rst(rst), 
      .q({net_871, net_827, net_919, net_935, net_951, net_967, net_983, 
      net_999}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_5(.clk(clk), .d(w_data[7:0]), .en(net_760), .rst(rst), 
      .q({net_870, net_826, net_918, net_934, net_950, net_966, net_982, 
      net_998}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_6(.clk(clk), .d(w_data[7:0]), .en(net_765), .rst(rst), 
      .q({net_869, net_825, net_917, net_933, net_949, net_965, net_981, 
      net_997}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_7(.clk(clk), .d(w_data[7:0]), .en(net_778), .rst(rst), 
      .q({net_868, net_824, net_916, net_932, net_948, net_964, net_980, 
      net_996}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_8(.clk(clk), .d(w_data[7:0]), .en(net_734), .rst(rst), 
      .q({net_867, net_823, net_915, net_931, net_947, net_963, net_979, 
      net_995}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_9(.clk(clk), .d(w_data[7:0]), .en(net_733), .rst(rst), 
      .q({net_866, net_822, net_914, net_930, net_946, net_962, net_978, 
      net_994}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_10(.clk(clk), .d(w_data[7:0]), .en(net_732), .rst(rst), 
      .q({net_865, net_821, net_1916, net_929, net_945, net_961, net_977, 
      net_993}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_11(.clk(clk), .d(w_data[7:0]), .en(net_731), .rst(rst), 
      .q({net_864, net_820, net_912, net_928, net_944, net_960, net_976, 
      net_992}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_12(.clk(clk), .d(w_data[7:0]), .en(net_725), .rst(rst), 
      .q({net_863, net_819, net_911, net_927, net_943, net_959, net_975, 
      net_991}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_13(.clk(clk), .d(w_data[7:0]), .en(net_723), .rst(rst), 
      .q({net_862, net_818, net_910, net_926, net_942, net_958, net_974, 
      net_990}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_14(.clk(clk), .d(w_data[7:0]), .en(net_720), .rst(rst), 
      .q({net_861, net_814, net_909, net_925, net_941, net_957, net_973, 
      net_989}), .vdd(vdd), .gnd(gnd));
  memory__reg8 reg8_15(.clk(clk), .d(w_data[7:0]), .en(net_718), .rst(rst), 
      .q({net_860, net_812, net_908, net_924, net_940, net_956, net_972, 
      net_988}), .vdd(vdd), .gnd(gnd));
endmodule   /* memory__regfile16 */

module lisp_coproc(addr, clk, cs, data_in, rst, rw, data_out, vdd, gnd);
  input [2:0] addr;
  input clk;
  input cs;
  input [7:0] data_in;
  input rst;
  input rw;
  output [7:0] data_out;
  input vdd;
  input gnd;

  supply1 vdd;
  supply0 gnd;
  wire fsm_0_alu_en, net_63, net_65, net_67, net_139, net_141, net_143, net_172;
  wire net_204, net_207, net_214, net_219, net_221, net_223, net_227, net_228;
  wire net_240, net_241, net_242, net_243, net_244, net_266, net_299, net_301;
  wire net_372, net_374, net_377, net_378, net_381, net_382, net_385, net_393;
  wire net_465, net_467, net_534, net_547, net_564, net_569, net_579, net_587;
  wire net_591, net_634, net_645, net_646, net_652, net_653, net_654, net_668;
  wire net_703, net_704, net_707, net_708, net_710, net_713, net_714, net_717;
  wire net_718, net_721, net_722, net_725, net_772, net_773, net_774, net_820;
  wire net_1043, net_1083, net_1182, net_1183, net_1184, net_1493, net_1498;
  wire net_1502, net_1504;
  wire [7:3] ioreg5_0_q_opcode;

  memory__bumpallocator bumpallo_0(.clk(clk), .rst(rst), .inc_en(net_266), 
      .ptr({net_652, net_653, net_654, net_634}), .vdd(vdd), .gnd(gnd));
  datapath__eq_8bit eq_8bit_0(.a({net_708, net_707, net_704, net_703, net_774, 
      net_773, net_772, net_820}), .b({net_710, net_725, net_722, net_721, 
      net_718, net_717, net_714, net_713}), .eq(net_587), .vdd(vdd), 
      .gnd(gnd));
  control__fsm fsm_0(.a(addr[2:0]), .clk(clk), .cs(cs), .op({net_1184, 
      net_1183, net_1182}), .rst(rst), .rw(rw), .alu_en(fsm_0_alu_en), 
      .busy(net_1502), .heap_wen(net_1504), .q_exec_cdr(net_1493), 
      .reg_wen(net_1498), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_0(.x(net_1184), .y(net_301), .vdd(vdd), .gnd(gnd));
  stdcells__inv inv_1(.x(net_299), .y(net_266), .vdd(vdd), .gnd(gnd));
  memory__ioreg5 ioreg5_0(.a(addr[2:0]), .clk(clk), .data_in(data_in[7:0]), 
      .data_out(data_out[0:0]), .global_en(cs), .reg_wen(net_1498), 
      .result_in({net_172, net_207, net_204, net_240, net_241, net_242, 
      net_243, net_244}), .rst(rst), .status_busy(net_1502), 
      .status_carry(net_1043), .status_err_heap(net_668), 
      .status_err_type(net_668), .status_zero(net_587), 
      .data_out_1(data_out[7:1]), .q_arg1({net_708, net_707, net_704, net_703, 
      net_774, net_773, net_772, net_820}), .q_arg2({net_710, net_725, net_722, 
      net_721, net_718, net_717, net_714, net_713}), 
      .q_opcode({ioreg5_0_q_opcode[7], ioreg5_0_q_opcode[6], 
      ioreg5_0_q_opcode[5], ioreg5_0_q_opcode[4], ioreg5_0_q_opcode[3], 
      net_1184, net_1183, net_1182}), .gnd(gnd), .vdd(vdd));
  stdcells__mux2 mux2_0(.i({net_587, net_579}), .s(net_1182), .z(net_591), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux2_8bit mux2_8bi_0(.i0({net_708, net_707, net_704, net_703, 
      net_774, net_773, net_772, net_820}), .i1({net_710, net_725, net_722, 
      net_721, net_718, net_717, net_714, net_713}), .s(net_1493), .z({net_219, 
      net_221, net_223, net_227, net_228, net_143, net_141, net_139}), 
      .vdd(vdd), .gnd(gnd));
  datapath__mux3_4bit mux3_4bi_0(.i0({net_774, net_773, net_772, net_820}), 
      .i1({net_652, net_653, net_654, net_634}), .i2({net_652, net_653, 
      net_654, net_634}), .s({net_1493, net_1504}), .z({net_214, net_63, 
      net_65, net_67}), .vdd(vdd), .gnd(gnd));
  datapath__mux4_8bit mux4_8bi_0(.i0({net_393, net_372, net_374, net_377, 
      net_378, net_381, net_382, net_385}), .i1({net_467, net_467, net_465, 
      net_465, net_652, net_653, net_654, net_634}), .i2({net_467, net_465, 
      net_534, net_547, net_646, net_645, net_564, net_569}), .i3({net_465, 
      net_591, net_465, net_465, net_465, net_465, net_465, net_591}), 
      .s({net_1184, net_1182}), .z({net_172, net_207, net_204, net_240, 
      net_241, net_242, net_243, net_244}), .vdd(vdd), .gnd(gnd));
  stdcells__nand2 nand2_0(.x(net_707), .y(net_708), .z(net_579), .vdd(vdd), 
      .gnd(gnd));
  stdcells__nand3 nand3_0(.w(net_1498), .x(net_301), .y(net_1182), .z(net_299), 
      .vdd(vdd), .gnd(gnd));
  datapath__rca_6bit rca_6bit_0(.a({net_704, net_703, net_774, net_773, 
      net_772, net_820}), .b({net_722, net_721, net_718, net_717, net_714, 
      net_713}), .cin(net_1083), .cout(net_1043), .s({net_534, net_547, 
      net_646, net_645, net_564, net_569}), .vdd(vdd), .gnd(gnd));
  memory__regfile16 regfile1_0(.clk(clk), .r_addr({net_774, net_773, net_772, 
      net_820}), .rst(rst), .w_addr({net_214, net_63, net_65, net_67}), 
      .w_data({net_219, net_221, net_223, net_227, net_228, net_143, net_141, 
      net_139}), .w_en(net_1504), .r_data({net_393, net_372, net_374, net_377, 
      net_378, net_381, net_382, net_385}), .vdd(vdd), .gnd(gnd));
  stdcells__tiehigh tiehigh_0(.y(net_467), .vdd(vdd), .gnd(gnd));
  stdcells__tielow tielow_0(.y(net_465), .vdd(vdd), .gnd(gnd));
  stdcells__tielow tielow_1(.y(net_668), .vdd(vdd), .gnd(gnd));
  stdcells__tielow tielow_2(.y(net_1083), .vdd(vdd), .gnd(gnd));
endmodule   /* lisp_coproc */