eel3792c_rv32i

RV32I implementation on a DE10-Lite FPGA for the EEL3792C course.
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CEL_PROJECT.v (895B)

      1 module CEL_PROJECT(
      2 
      3 	//////////// CLOCK //////////
      4 	input 		          		ADC_CLK_10,
      5 	input 		          		MAX10_CLK1_50,
      6 	input 		          		MAX10_CLK2_50,
      7 
      8 	//////////// SEG7 //////////
      9 	output		     [7:0]		HEX0,
     10 	output		     [7:0]		HEX1,
     11 	output		     [7:0]		HEX2,
     12 	output		     [7:0]		HEX3,
     13 	output		     [7:0]		HEX4,
     14 	output		     [7:0]		HEX5,
     15 
     16 	//////////// KEY //////////
     17 	input 		     [1:0]		KEY,
     18 
     19 	//////////// LED //////////
     20 	output		     [9:0]		LEDR,
     21 
     22 	//////////// SW //////////
     23 	input 		     [9:0]		SW,
     24 
     25 	//////////// GPIO, GPIO connect to GPIO Default //////////
     26 	inout 		    [35:0]		GPIO
     27 );
     28 
     29 
     30 wire [31:0] my_PC, my_rd;
     31 
     32 assign clk = ~KEY[1]; //ADC_CLK_10;
     33 
     34 my_computer U1(.clk(clk), .reset(~KEY[0]), .my_sw(SW[7:0]), .my_rd(my_rd), .my_PC(my_PC));		// Excluding comments 200+ lines of "code"
     35 
     36 assign LEDR = SW[9] ? my_PC : my_rd;
     37 
     38 endmodule