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AgeCommit message (Collapse)Author
2024-09-01add basic implementation of ppu write registersHEADmastervin
2024-09-01add basic ppu register readingvin
2024-09-01start working on ppuvin
2024-09-01add preliminary apu register supportvin
2024-08-31add shell.nix to get dependencies easilyvin
2024-08-21added snippet explaining the NES's 6502 variant and long-term goal for the ↵vin
project
2024-08-21update READMEvin
2024-07-21rename struct Rom to struct romvin
2024-07-21start implementing PPUvin
2024-07-21add CFLAGSvin
2024-07-20fix rest of logging format issuesvin
Now the format perfectly matches nestest.log. The only mismatch is now at the unimplemented APU memory addresses.
2024-07-20fix status flag bug in ASL and ROLvin
2024-07-20replace tabs with spaces to better match nestest.logvin
2024-07-07fix warnings and move cpu registers+flags to headervin
2024-07-04add nestest.nes and log that was used for testing the CPUvin
2024-07-04implement all of the nestest unofficial opcodes and fix branch cyclesvin
2024-07-04add preliminary implementation of the unofficial opcodesvin
2024-07-04start implementing unofficial opcodesvin
2024-07-04achieve cycle accuracy for official opcodesvin
Now, the unofficial opcodes can be implemented, and then the PPU and APU.
2024-07-03finalize trace logging to match nestest.log minus PPU cyclesvin
2024-07-03improve branching cycle accuracyvin
2024-07-03fix SBC bug in the rewrite and improve loggingvin
2024-07-03call opcode function pointer instead of using switch casevin
Also improve logging.
2024-06-30start refactoring opcode defs into an arrayvin
2024-06-30combine macro for updating N and Z status flagsvin
2024-06-30fix alignment of logging with ABS_X and ZP_Xvin
2024-06-30fix indirect JMP bug where the high byte does not increment out of pagevin
https://old.reddit.com/r/EmuDev/comments/15plfes/having_an_issue_with_nestest_on_my_6502_emulator/jvyck7k/ With this, it seems that all official opcodes run as nestest expects. Now, it's the unofficial opcodes that need to be implemented.
2024-06-30fix incorrect argument for INCvin
Perhaps a refactor is in order for the arguments to the opcodes.
2024-06-30rename README to README.mdvin
2024-06-30fix incorrect argument for ASL and LSRvin
2024-06-30fix JSR, RTS, and RTIvin
JSR was pushing 1 too high PC and RTS was 1 too low RTI was only pulling the low byte of PC
2024-06-30change SBC to be ADC with one's complement instead of two'svin
It seems that is what was expected when run with nestest.
2024-06-29fix status flag ordering shenanigansvin
2024-06-29fix ADC bug where V is calculated with new A instead of old Avin
2024-06-28fix status register to match nestestvin
2024-06-28improve logging and JMP indirectvin
2024-06-28fix more bugsvin
2024-06-28fix JSR and RTS bugvin
The stack's PUSH and PULL weren't proper and JSR was reading wrong argument it seems.
2024-06-28start logging instructions as nestest.log has donevin
2024-06-17start fixing bugs with memory accessvin
So this is why tests should be written while writing the program and instructions instead of all at once later. If this were all to be rewritten (which it probably will), I should add tests for each opcode instead of waiting until the end for ROM loading support.
2024-06-17implement basic iNES and Mapper 0 ROM loadingvin
It seems like the test ROM loads fine but the instructions are not, but that's exactly what the test ROM is for I suppose.
2024-06-16replace bit comparisons with 0 from greater than to not equalvin
They're both the same and the compiler might have already optimized it away. It also conveys the message better in my opinion.
2024-06-11add memory mirroring for system and ppu memoryvin
2024-06-11add separate implied/accumulator functions for certain opcodesvin
2024-06-11remove opcode json converter helper scriptsvin
They were only used to automate writing the boilerplate for each instruction. They're not needed at the moment and they were using 65c02 instructions instead of 6502 anyways.
2024-06-10add jsr, rti, rtsvin
2024-06-10implement untested most of stack-related opcodesvin
2024-06-10add lsr, rol, rorvin
2024-06-10implement tay, txa, tyavin
2024-06-10implement sta, stx, styvin