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authorvin <git@vineetk.net>2024-06-30 19:10:29 -0400
committervin <git@vineetk.net>2024-06-30 19:10:29 -0400
commita4b39966aed8d41ad4ddc6700683c4779e8d1cb2 (patch)
tree8fab3574f3d83199a4965ffecd0db549105ff96c
parentf28733401ebfe5457a4a79a37fbd5d2001de90bd (diff)
start refactoring opcode defs into an array
Diffstat
-rw-r--r--cpu.c18
-rw-r--r--cpu.h62
-rw-r--r--opcodes.h184
3 files changed, 248 insertions, 16 deletions
diff --git a/cpu.c b/cpu.c
index 0bbbc75..edfe172 100644
--- a/cpu.c
+++ b/cpu.c
@@ -4,6 +4,8 @@
4#include <stdlib.h> 4#include <stdlib.h>
5#include <string.h> 5#include <string.h>
6 6
7#include "cpu.h"
8#include "opcodes.h"
7#include "rom.h" 9#include "rom.h"
8 10
9#define MAX(a, b) ((a > b) ? a : b) 11#define MAX(a, b) ((a > b) ? a : b)
@@ -52,22 +54,6 @@ struct registers regs = {0};
52 54
53struct Rom rom = {0}; 55struct Rom rom = {0};
54 56
55enum addressing_mode {
56 AM_ACC,
57 AM_IMPLICIT,
58 AM_IMM,
59 AM_ZP,
60 AM_ZP_X,
61 AM_ZP_Y,
62 AM_REL,
63 AM_ABS,
64 AM_ABS_X,
65 AM_ABS_Y,
66 AM_IND,
67 AM_IND_X,
68 AM_IND_Y,
69};
70
71/* 64K address space, 16bit words */ 57/* 64K address space, 16bit words */
72uint8_t memory[0x16000]; 58uint8_t memory[0x16000];
73 59
diff --git a/cpu.h b/cpu.h
new file mode 100644
index 0000000..139ad83
--- /dev/null
+++ b/cpu.h
@@ -0,0 +1,62 @@
1#include <stdint.h>
2
3void ADC(uint16_t arg);
4void AND(uint16_t arg);
5void ASL_acc(uint16_t arg);
6void ASL(uint16_t arg);
7void BCC(uint16_t arg);
8void BCS(uint16_t arg);
9void BEQ(uint16_t arg);
10void BIT(uint16_t arg);
11void BMI(uint16_t arg);
12void BNE(uint16_t arg);
13void BPL(uint16_t arg);
14void BRK(uint16_t arg);
15void BVC(uint16_t arg);
16void BVS(uint16_t arg);
17void CLC(uint16_t arg);
18void CLD(uint16_t arg);
19void CLI(uint16_t arg);
20void CLV(uint16_t arg);
21void CMP(uint16_t arg);
22void CPX(uint16_t arg);
23void CPY(uint16_t arg);
24void DEC(uint16_t arg);
25void DEX(uint16_t arg);
26void DEY(uint16_t arg);
27void EOR(uint16_t arg);
28void INC(uint16_t arg);
29void INX(uint16_t arg);
30void INY(uint16_t arg);
31void JMP(uint16_t arg);
32void JSR(uint16_t arg);
33void LDA(uint16_t arg);
34void LDX(uint16_t arg);
35void LDY(uint16_t arg);
36void LSR_acc(uint16_t arg);
37void LSR(uint16_t arg);
38void NOP(uint16_t arg);
39void ORA(uint16_t arg);
40void PHA(uint16_t arg);
41void PHP(uint16_t arg);
42void PLA(uint16_t arg);
43void PLP(uint16_t arg);
44void ROL_acc(uint16_t arg);
45void ROL(uint16_t arg);
46void ROR_acc(uint16_t arg);
47void ROR(uint16_t arg);
48void RTI(uint16_t arg);
49void RTS(uint16_t arg);
50void SBC(uint16_t arg);
51void SEC(uint16_t arg);
52void SED(uint16_t arg);
53void SEI(uint16_t arg);
54void STA(uint16_t arg);
55void STX(uint16_t arg);
56void STY(uint16_t arg);
57void TAX(uint16_t arg);
58void TAY(uint16_t arg);
59void TSX(uint16_t arg);
60void TXA(uint16_t arg);
61void TXS(uint16_t arg);
62void TYA(uint16_t arg);
diff --git a/opcodes.h b/opcodes.h
new file mode 100644
index 0000000..defc427
--- /dev/null
+++ b/opcodes.h
@@ -0,0 +1,184 @@
1#include <stdint.h>
2
3#include "cpu.h"
4
5enum addressing_mode {
6 AM_NONE,
7 AM_ACC,
8 AM_IMM,
9 AM_REL,
10 AM_ZP,
11 AM_ZP_X,
12 AM_ZP_Y,
13 AM_ABS,
14 AM_ABS_X,
15 AM_ABS_Y,
16 AM_IND,
17 AM_IND_X,
18 AM_IND_Y,
19};
20
21/* index of below array is the code of the instruction */
22struct opcode {
23 const char name[4];
24 /* I know 16bit seems wasteful, but some ops use 16bit memory as arg */
25 void (*instr)(uint16_t arg);
26 uint8_t bytes;
27 uint8_t cycles;
28 enum addressing_mode mode;
29};
30
31struct opcode opcodes[0x100] = {
32 /* official opcodes */
33 [0x69] = { "ADC", ADC, 2, 2, AM_IMM },
34 [0x65] = { "ADC", ADC, 2, 3, AM_ZP },
35 [0x75] = { "ADC", ADC, 2, 4, AM_ZP_X },
36 [0x6D] = { "ADC", ADC, 3, 4, AM_ABS },
37 [0x7D] = { "ADC", ADC, 3, 4, AM_ABS_X },
38 [0x79] = { "ADC", ADC, 3, 4, AM_ABS_Y },
39 [0x61] = { "ADC", ADC, 2, 6, AM_IND_X },
40 [0x71] = { "ADC", ADC, 2, 5, AM_IND_Y },
41 [0x29] = { "AND", AND, 2, 2, AM_IMM },
42 [0x25] = { "AND", AND, 2, 3, AM_ZP },
43 [0x35] = { "AND", AND, 2, 4, AM_ZP_X },
44 [0x2D] = { "AND", AND, 3, 4, AM_ABS },
45 [0x3D] = { "AND", AND, 3, 4, AM_ABS_X },
46 [0x39] = { "AND", AND, 3, 4, AM_ABS_Y },
47 [0x21] = { "AND", AND, 2, 6, AM_IND_X },
48 [0x31] = { "AND", AND, 2, 5, AM_IND_Y },
49 [0x0A] = { "ASL", ASL_acc, 1, 2, AM_ACC },
50 [0x06] = { "ASL", ASL, 2, 5, AM_ZP },
51 [0x16] = { "ASL", ASL, 2, 6, AM_ZP_X },
52 [0x0E] = { "ASL", ASL, 3, 6, AM_ABS },
53 [0x1E] = { "ASL", ASL, 3, 7, AM_ABS_X },
54 [0x90] = { "BCC", BCC, 2, 2, AM_REL },
55 [0xB0] = { "BCS", BCS, 2, 2, AM_REL },
56 [0xF0] = { "BEQ", BEQ, 2, 2, AM_REL },
57 [0x24] = { "BIT", BIT, 2, 3, AM_ZP },
58 [0x2C] = { "BIT", BIT, 3, 4, AM_ABS },
59 [0x30] = { "BMI", BMI, 2, 2, AM_REL },
60 [0xD0] = { "BNE", BNE, 2, 2, AM_REL },
61 [0x10] = { "BPL", BPL, 2, 2, AM_REL },
62 [0x00] = { "BRK", BRK, 1, 7, AM_NONE },
63 [0x50] = { "BVC", BVC, 2, 2, AM_REL },
64 [0x70] = { "BVS", BVS, 2, 2, AM_REL },
65 [0x18] = { "CLC", CLC, 1, 2, AM_NONE },
66 [0xD8] = { "CLD", CLD, 1, 2, AM_NONE },
67 [0x58] = { "CLI", CLI, 1, 2, AM_NONE },
68 [0xB8] = { "CLV", CLV, 1, 2, AM_NONE },
69 [0xC9] = { "CMP", CMP, 2, 2, AM_IMM },
70 [0xC5] = { "CMP", CMP, 2, 3, AM_ZP },
71 [0xD5] = { "CMP", CMP, 2, 4, AM_ZP_X },
72 [0xCD] = { "CMP", CMP, 3, 4, AM_ABS },
73 [0xDD] = { "CMP", CMP, 3, 4, AM_ABS_X },
74 [0xD9] = { "CMP", CMP, 3, 4, AM_ABS_Y },
75 [0xC1] = { "CMP", CMP, 2, 6, AM_IND_X },
76 [0xD1] = { "CMP", CMP, 2, 5, AM_IND_Y },
77 [0xE0] = { "CPX", CPX, 2, 2, AM_IMM },
78 [0xE4] = { "CPX", CPX, 2, 3, AM_ZP },
79 [0xEC] = { "CPX", CPX, 3, 4, AM_ABS },
80 [0xC0] = { "CPY", CPY, 2, 2, AM_IMM },
81 [0xC4] = { "CPY", CPY, 2, 3, AM_ZP },
82 [0xCC] = { "CPY", CPY, 3, 4, AM_ABS },
83 [0xC6] = { "DEC", DEC, 2, 5, AM_ZP },
84 [0xD6] = { "DEC", DEC, 2, 6, AM_ZP_X },
85 [0xCE] = { "DEC", DEC, 3, 6, AM_ABS },
86 [0xDE] = { "DEC", DEC, 3, 7, AM_ABS_X },
87 [0xCA] = { "DEX", DEX, 1, 2, AM_NONE },
88 [0x88] = { "DEY", DEY, 1, 2, AM_NONE },
89 [0x49] = { "EOR", EOR, 2, 2, AM_IMM },
90 [0x45] = { "EOR", EOR, 2, 3, AM_ZP },
91 [0x55] = { "EOR", EOR, 2, 4, AM_ZP_X },
92 [0x4D] = { "EOR", EOR, 3, 4, AM_ABS },
93 [0x5D] = { "EOR", EOR, 3, 4, AM_ABS_X },
94 [0x59] = { "EOR", EOR, 3, 4, AM_ABS_Y },
95 [0x41] = { "EOR", EOR, 2, 6, AM_IND_X },
96 [0x51] = { "EOR", EOR, 2, 5, AM_IND_Y },
97 [0xE6] = { "INC", INC, 2, 5, AM_ZP },
98 [0xF6] = { "INC", INC, 2, 6, AM_ZP_X },
99 [0xEE] = { "INC", INC, 3, 6, AM_ABS },
100 [0xFE] = { "INC", INC, 3, 7, AM_ABS_X },
101 [0xE8] = { "INX", INX, 1, 2, AM_NONE },
102 [0xC8] = { "INY", INY, 1, 2, AM_NONE },
103 [0x4C] = { "JMP", JMP, 3, 3, AM_ABS },
104 [0x6C] = { "JMP", JMP, 3, 5, AM_IND },
105 [0x20] = { "JSR", JSR, 3, 6, AM_ABS },
106 [0xA9] = { "LDA", LDA, 2, 2, AM_IMM },
107 [0xA5] = { "LDA", LDA, 2, 3, AM_ZP },
108 [0xB5] = { "LDA", LDA, 2, 4, AM_ZP_X },
109 [0xAD] = { "LDA", LDA, 3, 4, AM_ABS },
110 [0xBD] = { "LDA", LDA, 3, 4, AM_ABS_X },
111 [0xB9] = { "LDA", LDA, 3, 4, AM_ABS_Y },
112 [0xA1] = { "LDA", LDA, 2, 6, AM_IND_X },
113 [0xB1] = { "LDA", LDA, 2, 5, AM_IND_Y },
114 [0xA2] = { "LDX", LDX, 2, 2, AM_IMM },
115 [0xA6] = { "LDX", LDX, 2, 3, AM_ZP },
116 [0xB6] = { "LDX", LDX, 2, 4, AM_ZP_Y },
117 [0xAE] = { "LDX", LDX, 3, 4, AM_ABS },
118 [0xBE] = { "LDX", LDX, 3, 4, AM_ABS_Y },
119 [0xA0] = { "LDY", LDY, 2, 2, AM_IMM },
120 [0xA4] = { "LDY", LDY, 2, 3, AM_ZP },
121 [0xB4] = { "LDY", LDY, 2, 4, AM_ZP_X },
122 [0xAC] = { "LDY", LDY, 3, 4, AM_ABS },
123 [0xBC] = { "LDY", LDY, 3, 4, AM_ABS_X },
124 [0x4A] = { "LSR", LSR_acc, 1, 2, AM_ACC },
125 [0x46] = { "LSR", LSR, 2, 5, AM_ZP },
126 [0x56] = { "LSR", LSR, 2, 6, AM_ZP_X },
127 [0x4E] = { "LSR", LSR, 3, 6, AM_ABS },
128 [0x5E] = { "LSR", LSR, 3, 7, AM_ABS_X },
129 [0xEA] = { "NOP", NOP, 1, 2, AM_NONE },
130 [0x09] = { "ORA", ORA, 2, 2, AM_IMM },
131 [0x05] = { "ORA", ORA, 2, 3, AM_ZP },
132 [0x15] = { "ORA", ORA, 2, 4, AM_ZP_X },
133 [0x0D] = { "ORA", ORA, 3, 4, AM_ABS },
134 [0x1D] = { "ORA", ORA, 3, 4, AM_ABS_X },
135 [0x19] = { "ORA", ORA, 3, 4, AM_ABS_Y },
136 [0x01] = { "ORA", ORA, 2, 6, AM_IND_X },
137 [0x11] = { "ORA", ORA, 2, 5, AM_IND_Y },
138 [0x48] = { "PHA", PHA, 1, 3, AM_NONE },
139 [0x08] = { "PHP", PHP, 1, 3, AM_NONE },
140 [0x68] = { "PLA", PLA, 1, 4, AM_NONE },
141 [0x28] = { "PLP", PLP, 1, 4, AM_NONE },
142 [0x2A] = { "ROL", ROL_acc, 1, 2, AM_ACC },
143 [0x26] = { "ROL", ROL, 2, 5, AM_ZP },
144 [0x36] = { "ROL", ROL, 2, 6, AM_ZP_X },
145 [0x2E] = { "ROL", ROL, 3, 6, AM_ABS },
146 [0x3E] = { "ROL", ROL, 3, 7, AM_ABS_X },
147 [0x6A] = { "ROR", ROR_acc, 1, 2, AM_ACC },
148 [0x66] = { "ROR", ROR, 2, 5, AM_ZP },
149 [0x76] = { "ROR", ROR, 2, 6, AM_ZP_X },
150 [0x6E] = { "ROR", ROR, 3, 6, AM_ABS },
151 [0x7E] = { "ROR", ROR, 3, 7, AM_ABS_X },
152 [0x40] = { "RTI", RTI, 1, 6, AM_NONE },
153 [0x60] = { "RTS", RTS, 1, 6, AM_NONE },
154 [0xE9] = { "SBC", SBC, 2, 2, AM_IMM },
155 [0xE5] = { "SBC", SBC, 2, 3, AM_ZP },
156 [0xF5] = { "SBC", SBC, 2, 4, AM_ZP_X },
157 [0xED] = { "SBC", SBC, 3, 4, AM_ABS },
158 [0xFD] = { "SBC", SBC, 3, 4, AM_ABS_X },
159 [0xF9] = { "SBC", SBC, 3, 4, AM_ABS_Y },
160 [0xE1] = { "SBC", SBC, 2, 6, AM_IND_X },
161 [0xF1] = { "SBC", SBC, 2, 5, AM_IND_Y },
162 [0x38] = { "SEC", SEC, 1, 2, AM_NONE },
163 [0xF8] = { "SED", SED, 1, 2, AM_NONE },
164 [0x78] = { "SEI", SEI, 1, 2, AM_NONE },
165 [0x85] = { "STA", STA, 2, 3, AM_ZP },
166 [0x95] = { "STA", STA, 2, 4, AM_ZP_X },
167 [0x8D] = { "STA", STA, 3, 4, AM_ABS },
168 [0x9D] = { "STA", STA, 3, 5, AM_ABS_X },
169 [0x99] = { "STA", STA, 3, 5, AM_ABS_Y },
170 [0x81] = { "STA", STA, 2, 6, AM_IND_X },
171 [0x91] = { "STA", STA, 2, 6, AM_IND_Y },
172 [0x86] = { "STX", STX, 2, 3, AM_ZP },
173 [0x96] = { "STX", STX, 2, 4, AM_ZP_Y },
174 [0x8E] = { "STX", STX, 3, 4, AM_ABS },
175 [0x84] = { "STY", STY, 2, 3, AM_ZP },
176 [0x94] = { "STY", STY, 2, 4, AM_ZP_X },
177 [0x8C] = { "STY", STY, 3, 4, AM_ABS },
178 [0xAA] = { "TAX", TAX, 1, 2, AM_NONE },
179 [0xA8] = { "TAY", TAY, 1, 2, AM_NONE },
180 [0xBA] = { "TSX", TSX, 1, 2, AM_NONE },
181 [0x8A] = { "TXA", TXA, 1, 2, AM_NONE },
182 [0x9A] = { "TXS", TXS, 1, 2, AM_NONE },
183 [0x98] = { "TYA", TYA, 1, 2, AM_NONE },
184};
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-03 04:51:25 +0000