diff options
| author | vin <git@vineetk.net> | 2024-07-04 12:11:53 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2024-07-04 12:11:53 -0400 |
| commit | c4fc40a036293a8f5899800ad3ecb1d24ba77bc4 (patch) | |
| tree | dc81c2ffd74287ef8f9867e50e463513641680fb | |
| parent | 5cd467eaf6b4f15f28b98c5fa49ab788dac945b3 (diff) | |
start implementing unofficial opcodes
| -rw-r--r-- | cpu.c | 149 | ||||
| -rw-r--r-- | cpu.h | 27 | ||||
| -rw-r--r-- | opcodes.h | 411 |
3 files changed, 434 insertions, 153 deletions
| @@ -177,6 +177,8 @@ branch(uint16_t addr, bool cond) | |||
| 177 | regs.pc = addr; | 177 | regs.pc = addr; |
| 178 | } | 178 | } |
| 179 | 179 | ||
| 180 | /* OFFICIAL OPCODES */ | ||
| 181 | |||
| 180 | void | 182 | void |
| 181 | ADC(uint16_t arg) | 183 | ADC(uint16_t arg) |
| 182 | { | 184 | { |
| @@ -696,6 +698,140 @@ TYA(uint16_t arg) | |||
| 696 | STATUS_UPDATE_NZ(regs.a); | 698 | STATUS_UPDATE_NZ(regs.a); |
| 697 | } | 699 | } |
| 698 | 700 | ||
| 701 | /* UNOFFICIAL OPCODES */ | ||
| 702 | |||
| 703 | void | ||
| 704 | AAC(uint16_t arg) | ||
| 705 | { | ||
| 706 | NOP(0); | ||
| 707 | } | ||
| 708 | |||
| 709 | void | ||
| 710 | AAX(uint16_t arg) | ||
| 711 | { | ||
| 712 | NOP(0); | ||
| 713 | } | ||
| 714 | |||
| 715 | void | ||
| 716 | ARR(uint16_t arg) | ||
| 717 | { | ||
| 718 | NOP(0); | ||
| 719 | } | ||
| 720 | |||
| 721 | void | ||
| 722 | ASR(uint16_t arg) | ||
| 723 | { | ||
| 724 | NOP(0); | ||
| 725 | } | ||
| 726 | |||
| 727 | void | ||
| 728 | ATX(uint16_t arg) | ||
| 729 | { | ||
| 730 | NOP(0); | ||
| 731 | } | ||
| 732 | |||
| 733 | void | ||
| 734 | AXA(uint16_t arg) | ||
| 735 | { | ||
| 736 | NOP(0); | ||
| 737 | } | ||
| 738 | |||
| 739 | void | ||
| 740 | AXS(uint16_t arg) | ||
| 741 | { | ||
| 742 | NOP(0); | ||
| 743 | } | ||
| 744 | |||
| 745 | void | ||
| 746 | DCP(uint16_t arg) | ||
| 747 | { | ||
| 748 | NOP(0); | ||
| 749 | } | ||
| 750 | |||
| 751 | void | ||
| 752 | DOP(uint16_t arg) | ||
| 753 | { | ||
| 754 | NOP(0); | ||
| 755 | } | ||
| 756 | |||
| 757 | void | ||
| 758 | ISC(uint16_t arg) | ||
| 759 | { | ||
| 760 | NOP(0); | ||
| 761 | } | ||
| 762 | |||
| 763 | void | ||
| 764 | KIL(uint16_t arg) | ||
| 765 | { | ||
| 766 | NOP(0); | ||
| 767 | } | ||
| 768 | |||
| 769 | void | ||
| 770 | LAR(uint16_t arg) | ||
| 771 | { | ||
| 772 | NOP(0); | ||
| 773 | } | ||
| 774 | |||
| 775 | void | ||
| 776 | LAX(uint16_t arg) | ||
| 777 | { | ||
| 778 | NOP(0); | ||
| 779 | } | ||
| 780 | |||
| 781 | void | ||
| 782 | RLA(uint16_t arg) | ||
| 783 | { | ||
| 784 | NOP(0); | ||
| 785 | } | ||
| 786 | |||
| 787 | void | ||
| 788 | RRA(uint16_t arg) | ||
| 789 | { | ||
| 790 | NOP(0); | ||
| 791 | } | ||
| 792 | |||
| 793 | void | ||
| 794 | SLO(uint16_t arg) | ||
| 795 | { | ||
| 796 | NOP(0); | ||
| 797 | } | ||
| 798 | |||
| 799 | void | ||
| 800 | SRE(uint16_t arg) | ||
| 801 | { | ||
| 802 | NOP(0); | ||
| 803 | } | ||
| 804 | |||
| 805 | void | ||
| 806 | SXA(uint16_t arg) | ||
| 807 | { | ||
| 808 | NOP(0); | ||
| 809 | } | ||
| 810 | |||
| 811 | void | ||
| 812 | SYA(uint16_t arg) | ||
| 813 | { | ||
| 814 | NOP(0); | ||
| 815 | } | ||
| 816 | |||
| 817 | void | ||
| 818 | TOP(uint16_t arg) | ||
| 819 | { | ||
| 820 | NOP(0); | ||
| 821 | } | ||
| 822 | |||
| 823 | void | ||
| 824 | XAA(uint16_t arg) | ||
| 825 | { | ||
| 826 | NOP(0); | ||
| 827 | } | ||
| 828 | |||
| 829 | void | ||
| 830 | XAS(uint16_t arg) | ||
| 831 | { | ||
| 832 | NOP(0); | ||
| 833 | } | ||
| 834 | |||
| 699 | static void | 835 | static void |
| 700 | interpret(void) | 836 | interpret(void) |
| 701 | { | 837 | { |
| @@ -711,7 +847,18 @@ interpret(void) | |||
| 711 | printf("%02X", op); | 847 | printf("%02X", op); |
| 712 | for (uint8_t i = 0; i < opcodes[op].bytes - 1; i++) | 848 | for (uint8_t i = 0; i < opcodes[op].bytes - 1; i++) |
| 713 | printf(" %02X", peek(regs.pc + i)); | 849 | printf(" %02X", peek(regs.pc + i)); |
| 714 | printf("\t%s ", opcodes[op].name); | 850 | |
| 851 | if (opcodes[op].unofficial) { | ||
| 852 | if (opcodes[op].bytes == 1) | ||
| 853 | printf(" "); | ||
| 854 | else if (opcodes[op].bytes == 2) | ||
| 855 | printf(" "); | ||
| 856 | else if (opcodes[op].bytes == 3) | ||
| 857 | putchar(' '); | ||
| 858 | putchar('*'); | ||
| 859 | } else | ||
| 860 | putchar('\t'); | ||
| 861 | printf("%s ", opcodes[op].name); | ||
| 715 | 862 | ||
| 716 | mode = opcodes[op].mode; | 863 | mode = opcodes[op].mode; |
| 717 | arg = opcode_mem(mode); | 864 | arg = opcode_mem(mode); |
| @@ -1,5 +1,6 @@ | |||
| 1 | #include <stdint.h> | 1 | #include <stdint.h> |
| 2 | 2 | ||
| 3 | /* OFFICIAL OPCODES */ | ||
| 3 | void ADC(uint16_t arg); | 4 | void ADC(uint16_t arg); |
| 4 | void AND(uint16_t arg); | 5 | void AND(uint16_t arg); |
| 5 | void ASL_acc(uint16_t arg); | 6 | void ASL_acc(uint16_t arg); |
| @@ -60,3 +61,29 @@ void TSX(uint16_t arg); | |||
| 60 | void TXA(uint16_t arg); | 61 | void TXA(uint16_t arg); |
| 61 | void TXS(uint16_t arg); | 62 | void TXS(uint16_t arg); |
| 62 | void TYA(uint16_t arg); | 63 | void TYA(uint16_t arg); |
| 64 | |||
| 65 | /* UNOFFICIAL OPCODES */ | ||
| 66 | void AAC(uint16_t arg); | ||
| 67 | void AAX(uint16_t arg); | ||
| 68 | void ARR(uint16_t arg); | ||
| 69 | void ASR(uint16_t arg); | ||
| 70 | void ATX(uint16_t arg); | ||
| 71 | void AXA(uint16_t arg); | ||
| 72 | void AXS(uint16_t arg); | ||
| 73 | void DCP(uint16_t arg); | ||
| 74 | void DOP(uint16_t arg); | ||
| 75 | void ISC(uint16_t arg); | ||
| 76 | void KIL(uint16_t arg); | ||
| 77 | void LAR(uint16_t arg); | ||
| 78 | void LAX(uint16_t arg); | ||
| 79 | void NOP(uint16_t arg); | ||
| 80 | void RLA(uint16_t arg); | ||
| 81 | void RRA(uint16_t arg); | ||
| 82 | void SBC(uint16_t arg); | ||
| 83 | void SLO(uint16_t arg); | ||
| 84 | void SRE(uint16_t arg); | ||
| 85 | void SXA(uint16_t arg); | ||
| 86 | void SYA(uint16_t arg); | ||
| 87 | void TOP(uint16_t arg); | ||
| 88 | void XAA(uint16_t arg); | ||
| 89 | void XAS(uint16_t arg); | ||
| @@ -29,160 +29,267 @@ struct opcode { | |||
| 29 | bool memread; | 29 | bool memread; |
| 30 | bool memwrite; | 30 | bool memwrite; |
| 31 | bool page_cross; | 31 | bool page_cross; |
| 32 | bool unofficial; | ||
| 32 | enum addressing_mode mode; | 33 | enum addressing_mode mode; |
| 33 | }; | 34 | }; |
| 34 | 35 | ||
| 35 | struct opcode opcodes[0x100] = { | 36 | struct opcode opcodes[0x100] = { |
| 36 | /* official opcodes */ | 37 | /* official opcodes: https://www.nesdev.org/obelisk-6502-guide/instructions.html */ |
| 37 | [0x69] = { "ADC", ADC, 2, 2, false, false, false, AM_IMM }, | 38 | [0x69] = { "ADC", ADC, 2, 2, false, false, false, false, AM_IMM }, |
| 38 | [0x65] = { "ADC", ADC, 2, 3, true, false, false, AM_ZP }, | 39 | [0x65] = { "ADC", ADC, 2, 3, true, false, false, false, AM_ZP }, |
| 39 | [0x75] = { "ADC", ADC, 2, 4, true, false, false, AM_ZP_X }, | 40 | [0x75] = { "ADC", ADC, 2, 4, true, false, false, false, AM_ZP_X }, |
| 40 | [0x6D] = { "ADC", ADC, 3, 4, true, false, false, AM_ABS }, | 41 | [0x6D] = { "ADC", ADC, 3, 4, true, false, false, false, AM_ABS }, |
| 41 | [0x7D] = { "ADC", ADC, 3, 4, true, false, true, AM_ABS_X }, | 42 | [0x7D] = { "ADC", ADC, 3, 4, true, false, true, false, AM_ABS_X }, |
| 42 | [0x79] = { "ADC", ADC, 3, 4, true, false, true, AM_ABS_Y }, | 43 | [0x79] = { "ADC", ADC, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 43 | [0x61] = { "ADC", ADC, 2, 6, true, false, false, AM_IND_X }, | 44 | [0x61] = { "ADC", ADC, 2, 6, true, false, false, false, AM_IND_X }, |
| 44 | [0x71] = { "ADC", ADC, 2, 5, true, false, true, AM_IND_Y }, | 45 | [0x71] = { "ADC", ADC, 2, 5, true, false, true, false, AM_IND_Y }, |
| 45 | [0x29] = { "AND", AND, 2, 2, false, false, false, AM_IMM }, | 46 | [0x29] = { "AND", AND, 2, 2, false, false, false, false, AM_IMM }, |
| 46 | [0x25] = { "AND", AND, 2, 3, true, false, false, AM_ZP }, | 47 | [0x25] = { "AND", AND, 2, 3, true, false, false, false, AM_ZP }, |
| 47 | [0x35] = { "AND", AND, 2, 4, true, false, false, AM_ZP_X }, | 48 | [0x35] = { "AND", AND, 2, 4, true, false, false, false, AM_ZP_X }, |
| 48 | [0x2D] = { "AND", AND, 3, 4, true, false, false, AM_ABS }, | 49 | [0x2D] = { "AND", AND, 3, 4, true, false, false, false, AM_ABS }, |
| 49 | [0x3D] = { "AND", AND, 3, 4, true, false, true, AM_ABS_X }, | 50 | [0x3D] = { "AND", AND, 3, 4, true, false, true, false, AM_ABS_X }, |
| 50 | [0x39] = { "AND", AND, 3, 4, true, false, true, AM_ABS_Y }, | 51 | [0x39] = { "AND", AND, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 51 | [0x21] = { "AND", AND, 2, 6, true, false, false, AM_IND_X }, | 52 | [0x21] = { "AND", AND, 2, 6, true, false, false, false, AM_IND_X }, |
| 52 | [0x31] = { "AND", AND, 2, 5, true, false, true, AM_IND_Y }, | 53 | [0x31] = { "AND", AND, 2, 5, true, false, true, false, AM_IND_Y }, |
| 53 | [0x0A] = { "ASL", ASL_acc, 1, 2, false, false, false, AM_ACC }, | 54 | [0x0A] = { "ASL", ASL_acc, 1, 2, false, false, false, false, AM_ACC }, |
| 54 | [0x06] = { "ASL", ASL, 2, 5, false, true, false, AM_ZP }, | 55 | [0x06] = { "ASL", ASL, 2, 5, false, true, false, false, AM_ZP }, |
| 55 | [0x16] = { "ASL", ASL, 2, 6, false, true, false, AM_ZP_X }, | 56 | [0x16] = { "ASL", ASL, 2, 6, false, true, false, false, AM_ZP_X }, |
| 56 | [0x0E] = { "ASL", ASL, 3, 6, false, true, false, AM_ABS }, | 57 | [0x0E] = { "ASL", ASL, 3, 6, false, true, false, false, AM_ABS }, |
| 57 | [0x1E] = { "ASL", ASL, 3, 7, false, true, false, AM_ABS_X }, | 58 | [0x1E] = { "ASL", ASL, 3, 7, false, true, false, false, AM_ABS_X }, |
| 58 | [0x90] = { "BCC", BCC, 2, 2, false, false, true, AM_REL }, | 59 | [0x90] = { "BCC", BCC, 2, 2, false, false, true, false, AM_REL }, |
| 59 | [0xB0] = { "BCS", BCS, 2, 2, false, false, true, AM_REL }, | 60 | [0xB0] = { "BCS", BCS, 2, 2, false, false, true, false, AM_REL }, |
| 60 | [0xF0] = { "BEQ", BEQ, 2, 2, false, false, true, AM_REL }, | 61 | [0xF0] = { "BEQ", BEQ, 2, 2, false, false, true, false, AM_REL }, |
| 61 | [0x24] = { "BIT", BIT, 2, 3, true, false, false, AM_ZP }, | 62 | [0x24] = { "BIT", BIT, 2, 3, true, false, false, false, AM_ZP }, |
| 62 | [0x2C] = { "BIT", BIT, 3, 4, true, false, false, AM_ABS }, | 63 | [0x2C] = { "BIT", BIT, 3, 4, true, false, false, false, AM_ABS }, |
| 63 | [0x30] = { "BMI", BMI, 2, 2, false, false, true, AM_REL }, | 64 | [0x30] = { "BMI", BMI, 2, 2, false, false, true, false, AM_REL }, |
| 64 | [0xD0] = { "BNE", BNE, 2, 2, false, false, true, AM_REL }, | 65 | [0xD0] = { "BNE", BNE, 2, 2, false, false, true, false, AM_REL }, |
| 65 | [0x10] = { "BPL", BPL, 2, 2, false, false, true, AM_REL }, | 66 | [0x10] = { "BPL", BPL, 2, 2, false, false, true, false, AM_REL }, |
| 66 | [0x00] = { "BRK", BRK, 1, 7, false, false, false, AM_NONE }, | 67 | [0x00] = { "BRK", BRK, 1, 7, false, false, false, false, AM_NONE }, |
| 67 | [0x50] = { "BVC", BVC, 2, 2, false, false, true, AM_REL }, | 68 | [0x50] = { "BVC", BVC, 2, 2, false, false, true, false, AM_REL }, |
| 68 | [0x70] = { "BVS", BVS, 2, 2, false, false, true, AM_REL }, | 69 | [0x70] = { "BVS", BVS, 2, 2, false, false, true, false, AM_REL }, |
| 69 | [0x18] = { "CLC", CLC, 1, 2, false, false, false, AM_NONE }, | 70 | [0x18] = { "CLC", CLC, 1, 2, false, false, false, false, AM_NONE }, |
| 70 | [0xD8] = { "CLD", CLD, 1, 2, false, false, false, AM_NONE }, | 71 | [0xD8] = { "CLD", CLD, 1, 2, false, false, false, false, AM_NONE }, |
| 71 | [0x58] = { "CLI", CLI, 1, 2, false, false, false, AM_NONE }, | 72 | [0x58] = { "CLI", CLI, 1, 2, false, false, false, false, AM_NONE }, |
| 72 | [0xB8] = { "CLV", CLV, 1, 2, false, false, false, AM_NONE }, | 73 | [0xB8] = { "CLV", CLV, 1, 2, false, false, false, false, AM_NONE }, |
| 73 | [0xC9] = { "CMP", CMP, 2, 2, false, false, false, AM_IMM }, | 74 | [0xC9] = { "CMP", CMP, 2, 2, false, false, false, false, AM_IMM }, |
| 74 | [0xC5] = { "CMP", CMP, 2, 3, true, false, false, AM_ZP }, | 75 | [0xC5] = { "CMP", CMP, 2, 3, true, false, false, false, AM_ZP }, |
| 75 | [0xD5] = { "CMP", CMP, 2, 4, true, false, false, AM_ZP_X }, | 76 | [0xD5] = { "CMP", CMP, 2, 4, true, false, false, false, AM_ZP_X }, |
| 76 | [0xCD] = { "CMP", CMP, 3, 4, true, false, false, AM_ABS }, | 77 | [0xCD] = { "CMP", CMP, 3, 4, true, false, false, false, AM_ABS }, |
| 77 | [0xDD] = { "CMP", CMP, 3, 4, true, false, true, AM_ABS_X }, | 78 | [0xDD] = { "CMP", CMP, 3, 4, true, false, true, false, AM_ABS_X }, |
| 78 | [0xD9] = { "CMP", CMP, 3, 4, true, false, true, AM_ABS_Y }, | 79 | [0xD9] = { "CMP", CMP, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 79 | [0xC1] = { "CMP", CMP, 2, 6, true, false, false, AM_IND_X }, | 80 | [0xC1] = { "CMP", CMP, 2, 6, true, false, false, false, AM_IND_X }, |
| 80 | [0xD1] = { "CMP", CMP, 2, 5, true, false, true, AM_IND_Y }, | 81 | [0xD1] = { "CMP", CMP, 2, 5, true, false, true, false, AM_IND_Y }, |
| 81 | [0xE0] = { "CPX", CPX, 2, 2, false, false, false, AM_IMM }, | 82 | [0xE0] = { "CPX", CPX, 2, 2, false, false, false, false, AM_IMM }, |
| 82 | [0xE4] = { "CPX", CPX, 2, 3, true, false, false, AM_ZP }, | 83 | [0xE4] = { "CPX", CPX, 2, 3, true, false, false, false, AM_ZP }, |
| 83 | [0xEC] = { "CPX", CPX, 3, 4, true, false, false, AM_ABS }, | 84 | [0xEC] = { "CPX", CPX, 3, 4, true, false, false, false, AM_ABS }, |
| 84 | [0xC0] = { "CPY", CPY, 2, 2, false, false, false, AM_IMM }, | 85 | [0xC0] = { "CPY", CPY, 2, 2, false, false, false, false, AM_IMM }, |
| 85 | [0xC4] = { "CPY", CPY, 2, 3, true, false, false, AM_ZP }, | 86 | [0xC4] = { "CPY", CPY, 2, 3, true, false, false, false, AM_ZP }, |
| 86 | [0xCC] = { "CPY", CPY, 3, 4, true, false, false, AM_ABS }, | 87 | [0xCC] = { "CPY", CPY, 3, 4, true, false, false, false, AM_ABS }, |
| 87 | [0xC6] = { "DEC", DEC, 2, 5, false, true, false, AM_ZP }, | 88 | [0xC6] = { "DEC", DEC, 2, 5, false, true, false, false, AM_ZP }, |
| 88 | [0xD6] = { "DEC", DEC, 2, 6, false, true, false, AM_ZP_X }, | 89 | [0xD6] = { "DEC", DEC, 2, 6, false, true, false, false, AM_ZP_X }, |
| 89 | [0xCE] = { "DEC", DEC, 3, 6, false, true, false, AM_ABS }, | 90 | [0xCE] = { "DEC", DEC, 3, 6, false, true, false, false, AM_ABS }, |
| 90 | [0xDE] = { "DEC", DEC, 3, 7, false, true, false, AM_ABS_X }, | 91 | [0xDE] = { "DEC", DEC, 3, 7, false, true, false, false, AM_ABS_X }, |
| 91 | [0xCA] = { "DEX", DEX, 1, 2, false, false, false, AM_NONE }, | 92 | [0xCA] = { "DEX", DEX, 1, 2, false, false, false, false, AM_NONE }, |
| 92 | [0x88] = { "DEY", DEY, 1, 2, false, false, false, AM_NONE }, | 93 | [0x88] = { "DEY", DEY, 1, 2, false, false, false, false, AM_NONE }, |
| 93 | [0x49] = { "EOR", EOR, 2, 2, false, false, false, AM_IMM }, | 94 | [0x49] = { "EOR", EOR, 2, 2, false, false, false, false, AM_IMM }, |
| 94 | [0x45] = { "EOR", EOR, 2, 3, true, false, false, AM_ZP }, | 95 | [0x45] = { "EOR", EOR, 2, 3, true, false, false, false, AM_ZP }, |
| 95 | [0x55] = { "EOR", EOR, 2, 4, true, false, false, AM_ZP_X }, | 96 | [0x55] = { "EOR", EOR, 2, 4, true, false, false, false, AM_ZP_X }, |
| 96 | [0x4D] = { "EOR", EOR, 3, 4, true, false, false, AM_ABS }, | 97 | [0x4D] = { "EOR", EOR, 3, 4, true, false, false, false, AM_ABS }, |
| 97 | [0x5D] = { "EOR", EOR, 3, 4, true, false, true, AM_ABS_X }, | 98 | [0x5D] = { "EOR", EOR, 3, 4, true, false, true, false, AM_ABS_X }, |
| 98 | [0x59] = { "EOR", EOR, 3, 4, true, false, true, AM_ABS_Y }, | 99 | [0x59] = { "EOR", EOR, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 99 | [0x41] = { "EOR", EOR, 2, 6, true, false, false, AM_IND_X }, | 100 | [0x41] = { "EOR", EOR, 2, 6, true, false, false, false, AM_IND_X }, |
| 100 | [0x51] = { "EOR", EOR, 2, 5, true, false, true, AM_IND_Y }, | 101 | [0x51] = { "EOR", EOR, 2, 5, true, false, true, false, AM_IND_Y }, |
| 101 | [0xE6] = { "INC", INC, 2, 5, false, true, false, AM_ZP }, | 102 | [0xE6] = { "INC", INC, 2, 5, false, true, false, false, AM_ZP }, |
| 102 | [0xF6] = { "INC", INC, 2, 6, false, true, false, AM_ZP_X }, | 103 | [0xF6] = { "INC", INC, 2, 6, false, true, false, false, AM_ZP_X }, |
| 103 | [0xEE] = { "INC", INC, 3, 6, false, true, false, AM_ABS }, | 104 | [0xEE] = { "INC", INC, 3, 6, false, true, false, false, AM_ABS }, |
| 104 | [0xFE] = { "INC", INC, 3, 7, false, true, false, AM_ABS_X }, | 105 | [0xFE] = { "INC", INC, 3, 7, false, true, false, false, AM_ABS_X }, |
| 105 | [0xE8] = { "INX", INX, 1, 2, false, false, false, AM_NONE }, | 106 | [0xE8] = { "INX", INX, 1, 2, false, false, false, false, AM_NONE }, |
| 106 | [0xC8] = { "INY", INY, 1, 2, false, false, false, AM_NONE }, | 107 | [0xC8] = { "INY", INY, 1, 2, false, false, false, false, AM_NONE }, |
| 107 | [0x4C] = { "JMP", JMP, 3, 3, false, false, false, AM_ABS }, | 108 | [0x4C] = { "JMP", JMP, 3, 3, false, false, false, false, AM_ABS }, |
| 108 | [0x6C] = { "JMP", JMP, 3, 5, false, false, false, AM_IND }, | 109 | [0x6C] = { "JMP", JMP, 3, 5, false, false, false, false, AM_IND }, |
| 109 | [0x20] = { "JSR", JSR, 3, 6, false, false, false, AM_ABS }, | 110 | [0x20] = { "JSR", JSR, 3, 6, false, false, false, false, AM_ABS }, |
| 110 | [0xA9] = { "LDA", LDA, 2, 2, false, false, false, AM_IMM }, | 111 | [0xA9] = { "LDA", LDA, 2, 2, false, false, false, false, AM_IMM }, |
| 111 | [0xA5] = { "LDA", LDA, 2, 3, true, false, false, AM_ZP }, | 112 | [0xA5] = { "LDA", LDA, 2, 3, true, false, false, false, AM_ZP }, |
| 112 | [0xB5] = { "LDA", LDA, 2, 4, true, false, false, AM_ZP_X }, | 113 | [0xB5] = { "LDA", LDA, 2, 4, true, false, false, false, AM_ZP_X }, |
| 113 | [0xAD] = { "LDA", LDA, 3, 4, true, false, false, AM_ABS }, | 114 | [0xAD] = { "LDA", LDA, 3, 4, true, false, false, false, AM_ABS }, |
| 114 | [0xBD] = { "LDA", LDA, 3, 4, true, false, true, AM_ABS_X }, | 115 | [0xBD] = { "LDA", LDA, 3, 4, true, false, true, false, AM_ABS_X }, |
| 115 | [0xB9] = { "LDA", LDA, 3, 4, true, false, true, AM_ABS_Y }, | 116 | [0xB9] = { "LDA", LDA, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 116 | [0xA1] = { "LDA", LDA, 2, 6, true, false, false, AM_IND_X }, | 117 | [0xA1] = { "LDA", LDA, 2, 6, true, false, false, false, AM_IND_X }, |
| 117 | [0xB1] = { "LDA", LDA, 2, 5, true, false, true, AM_IND_Y }, | 118 | [0xB1] = { "LDA", LDA, 2, 5, true, false, true, false, AM_IND_Y }, |
| 118 | [0xA2] = { "LDX", LDX, 2, 2, false, false, false, AM_IMM }, | 119 | [0xA2] = { "LDX", LDX, 2, 2, false, false, false, false, AM_IMM }, |
| 119 | [0xA6] = { "LDX", LDX, 2, 3, true, false, false, AM_ZP }, | 120 | [0xA6] = { "LDX", LDX, 2, 3, true, false, false, false, AM_ZP }, |
| 120 | [0xB6] = { "LDX", LDX, 2, 4, true, false, false, AM_ZP_Y }, | 121 | [0xB6] = { "LDX", LDX, 2, 4, true, false, false, false, AM_ZP_Y }, |
| 121 | [0xAE] = { "LDX", LDX, 3, 4, true, false, false, AM_ABS }, | 122 | [0xAE] = { "LDX", LDX, 3, 4, true, false, false, false, AM_ABS }, |
| 122 | [0xBE] = { "LDX", LDX, 3, 4, true, false, true, AM_ABS_Y }, | 123 | [0xBE] = { "LDX", LDX, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 123 | [0xA0] = { "LDY", LDY, 2, 2, false, false, false, AM_IMM }, | 124 | [0xA0] = { "LDY", LDY, 2, 2, false, false, false, false, AM_IMM }, |
| 124 | [0xA4] = { "LDY", LDY, 2, 3, true, false, false, AM_ZP }, | 125 | [0xA4] = { "LDY", LDY, 2, 3, true, false, false, false, AM_ZP }, |
| 125 | [0xB4] = { "LDY", LDY, 2, 4, true, false, false, AM_ZP_X }, | 126 | [0xB4] = { "LDY", LDY, 2, 4, true, false, false, false, AM_ZP_X }, |
| 126 | [0xAC] = { "LDY", LDY, 3, 4, true, false, false, AM_ABS }, | 127 | [0xAC] = { "LDY", LDY, 3, 4, true, false, false, false, AM_ABS }, |
| 127 | [0xBC] = { "LDY", LDY, 3, 4, true, false, true, AM_ABS_X }, | 128 | [0xBC] = { "LDY", LDY, 3, 4, true, false, true, false, AM_ABS_X }, |
| 128 | [0x4A] = { "LSR", LSR_acc, 1, 2, false, false, false, AM_ACC }, | 129 | [0x4A] = { "LSR", LSR_acc, 1, 2, false, false, false, false, AM_ACC }, |
| 129 | [0x46] = { "LSR", LSR, 2, 5, false, true, false, AM_ZP }, | 130 | [0x46] = { "LSR", LSR, 2, 5, false, true, false, false, AM_ZP }, |
| 130 | [0x56] = { "LSR", LSR, 2, 6, false, true, false, AM_ZP_X }, | 131 | [0x56] = { "LSR", LSR, 2, 6, false, true, false, false, AM_ZP_X }, |
| 131 | [0x4E] = { "LSR", LSR, 3, 6, false, true, false, AM_ABS }, | 132 | [0x4E] = { "LSR", LSR, 3, 6, false, true, false, false, AM_ABS }, |
| 132 | [0x5E] = { "LSR", LSR, 3, 7, false, true, false, AM_ABS_X }, | 133 | [0x5E] = { "LSR", LSR, 3, 7, false, true, false, false, AM_ABS_X }, |
| 133 | [0xEA] = { "NOP", NOP, 1, 2, false, false, false, AM_NONE }, | 134 | [0xEA] = { "NOP", NOP, 1, 2, false, false, false, false, AM_NONE }, |
| 134 | [0x09] = { "ORA", ORA, 2, 2, false, false, false, AM_IMM }, | 135 | [0x09] = { "ORA", ORA, 2, 2, false, false, false, false, AM_IMM }, |
| 135 | [0x05] = { "ORA", ORA, 2, 3, true, false, false, AM_ZP }, | 136 | [0x05] = { "ORA", ORA, 2, 3, true, false, false, false, AM_ZP }, |
| 136 | [0x15] = { "ORA", ORA, 2, 4, true, false, false, AM_ZP_X }, | 137 | [0x15] = { "ORA", ORA, 2, 4, true, false, false, false, AM_ZP_X }, |
| 137 | [0x0D] = { "ORA", ORA, 3, 4, true, false, false, AM_ABS }, | 138 | [0x0D] = { "ORA", ORA, 3, 4, true, false, false, false, AM_ABS }, |
| 138 | [0x1D] = { "ORA", ORA, 3, 4, true, false, true, AM_ABS_X }, | 139 | [0x1D] = { "ORA", ORA, 3, 4, true, false, true, false, AM_ABS_X }, |
| 139 | [0x19] = { "ORA", ORA, 3, 4, true, false, true, AM_ABS_Y }, | 140 | [0x19] = { "ORA", ORA, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 140 | [0x01] = { "ORA", ORA, 2, 6, true, false, false, AM_IND_X }, | 141 | [0x01] = { "ORA", ORA, 2, 6, true, false, false, false, AM_IND_X }, |
| 141 | [0x11] = { "ORA", ORA, 2, 5, true, false, true, AM_IND_Y }, | 142 | [0x11] = { "ORA", ORA, 2, 5, true, false, true, false, AM_IND_Y }, |
| 142 | [0x48] = { "PHA", PHA, 1, 3, false, false, false, AM_NONE }, | 143 | [0x48] = { "PHA", PHA, 1, 3, false, false, false, false, AM_NONE }, |
| 143 | [0x08] = { "PHP", PHP, 1, 3, false, false, false, AM_NONE }, | 144 | [0x08] = { "PHP", PHP, 1, 3, false, false, false, false, AM_NONE }, |
| 144 | [0x68] = { "PLA", PLA, 1, 4, false, false, false, AM_NONE }, | 145 | [0x68] = { "PLA", PLA, 1, 4, false, false, false, false, AM_NONE }, |
| 145 | [0x28] = { "PLP", PLP, 1, 4, false, false, false, AM_NONE }, | 146 | [0x28] = { "PLP", PLP, 1, 4, false, false, false, false, AM_NONE }, |
| 146 | [0x2A] = { "ROL", ROL_acc, 1, 2, false, false, false, AM_ACC }, | 147 | [0x2A] = { "ROL", ROL_acc, 1, 2, false, false, false, false, AM_ACC }, |
| 147 | [0x26] = { "ROL", ROL, 2, 5, false, true, false, AM_ZP }, | 148 | [0x26] = { "ROL", ROL, 2, 5, false, true, false, false, AM_ZP }, |
| 148 | [0x36] = { "ROL", ROL, 2, 6, false, true, false, AM_ZP_X }, | 149 | [0x36] = { "ROL", ROL, 2, 6, false, true, false, false, AM_ZP_X }, |
| 149 | [0x2E] = { "ROL", ROL, 3, 6, false, true, false, AM_ABS }, | 150 | [0x2E] = { "ROL", ROL, 3, 6, false, true, false, false, AM_ABS }, |
| 150 | [0x3E] = { "ROL", ROL, 3, 7, false, true, false, AM_ABS_X }, | 151 | [0x3E] = { "ROL", ROL, 3, 7, false, true, false, false, AM_ABS_X }, |
| 151 | [0x6A] = { "ROR", ROR_acc, 1, 2, false, false, false, AM_ACC }, | 152 | [0x6A] = { "ROR", ROR_acc, 1, 2, false, false, false, false, AM_ACC }, |
| 152 | [0x66] = { "ROR", ROR, 2, 5, false, true, false, AM_ZP }, | 153 | [0x66] = { "ROR", ROR, 2, 5, false, true, false, false, AM_ZP }, |
| 153 | [0x76] = { "ROR", ROR, 2, 6, false, true, false, AM_ZP_X }, | 154 | [0x76] = { "ROR", ROR, 2, 6, false, true, false, false, AM_ZP_X }, |
| 154 | [0x6E] = { "ROR", ROR, 3, 6, false, true, false, AM_ABS }, | 155 | [0x6E] = { "ROR", ROR, 3, 6, false, true, false, false, AM_ABS }, |
| 155 | [0x7E] = { "ROR", ROR, 3, 7, false, true, false, AM_ABS_X }, | 156 | [0x7E] = { "ROR", ROR, 3, 7, false, true, false, false, AM_ABS_X }, |
| 156 | [0x40] = { "RTI", RTI, 1, 6, false, false, false, AM_NONE }, | 157 | [0x40] = { "RTI", RTI, 1, 6, false, false, false, false, AM_NONE }, |
| 157 | [0x60] = { "RTS", RTS, 1, 6, false, false, false, AM_NONE }, | 158 | [0x60] = { "RTS", RTS, 1, 6, false, false, false, false, AM_NONE }, |
| 158 | [0xE9] = { "SBC", SBC, 2, 2, false, false, false, AM_IMM }, | 159 | [0xE9] = { "SBC", SBC, 2, 2, false, false, false, false, AM_IMM }, |
| 159 | [0xE5] = { "SBC", SBC, 2, 3, true, false, false, AM_ZP }, | 160 | [0xE5] = { "SBC", SBC, 2, 3, true, false, false, false, AM_ZP }, |
| 160 | [0xF5] = { "SBC", SBC, 2, 4, true, false, false, AM_ZP_X }, | 161 | [0xF5] = { "SBC", SBC, 2, 4, true, false, false, false, AM_ZP_X }, |
| 161 | [0xED] = { "SBC", SBC, 3, 4, true, false, false, AM_ABS }, | 162 | [0xED] = { "SBC", SBC, 3, 4, true, false, false, false, AM_ABS }, |
| 162 | [0xFD] = { "SBC", SBC, 3, 4, true, false, true, AM_ABS_X }, | 163 | [0xFD] = { "SBC", SBC, 3, 4, true, false, true, false, AM_ABS_X }, |
| 163 | [0xF9] = { "SBC", SBC, 3, 4, true, false, true, AM_ABS_Y }, | 164 | [0xF9] = { "SBC", SBC, 3, 4, true, false, true, false, AM_ABS_Y }, |
| 164 | [0xE1] = { "SBC", SBC, 2, 6, true, false, false, AM_IND_X }, | 165 | [0xE1] = { "SBC", SBC, 2, 6, true, false, false, false, AM_IND_X }, |
| 165 | [0xF1] = { "SBC", SBC, 2, 5, true, false, true, AM_IND_Y }, | 166 | [0xF1] = { "SBC", SBC, 2, 5, true, false, true, false, AM_IND_Y }, |
| 166 | [0x38] = { "SEC", SEC, 1, 2, false, false, false, AM_NONE }, | 167 | [0x38] = { "SEC", SEC, 1, 2, false, false, false, false, AM_NONE }, |
| 167 | [0xF8] = { "SED", SED, 1, 2, false, false, false, AM_NONE }, | 168 | [0xF8] = { "SED", SED, 1, 2, false, false, false, false, AM_NONE }, |
| 168 | [0x78] = { "SEI", SEI, 1, 2, false, false, false, AM_NONE }, | 169 | [0x78] = { "SEI", SEI, 1, 2, false, false, false, false, AM_NONE }, |
| 169 | [0x85] = { "STA", STA, 2, 3, false, true, false, AM_ZP }, | 170 | [0x85] = { "STA", STA, 2, 3, false, true, false, false, AM_ZP }, |
| 170 | [0x95] = { "STA", STA, 2, 4, false, true, false, AM_ZP_X }, | 171 | [0x95] = { "STA", STA, 2, 4, false, true, false, false, AM_ZP_X }, |
| 171 | [0x8D] = { "STA", STA, 3, 4, false, true, false, AM_ABS }, | 172 | [0x8D] = { "STA", STA, 3, 4, false, true, false, false, AM_ABS }, |
| 172 | [0x9D] = { "STA", STA, 3, 5, false, true, false, AM_ABS_X }, | 173 | [0x9D] = { "STA", STA, 3, 5, false, true, false, false, AM_ABS_X }, |
| 173 | [0x99] = { "STA", STA, 3, 5, false, true, false, AM_ABS_Y }, | 174 | [0x99] = { "STA", STA, 3, 5, false, true, false, false, AM_ABS_Y }, |
| 174 | [0x81] = { "STA", STA, 2, 6, false, true, false, AM_IND_X }, | 175 | [0x81] = { "STA", STA, 2, 6, false, true, false, false, AM_IND_X }, |
| 175 | [0x91] = { "STA", STA, 2, 6, false, true, false, AM_IND_Y }, | 176 | [0x91] = { "STA", STA, 2, 6, false, true, false, false, AM_IND_Y }, |
| 176 | [0x86] = { "STX", STX, 2, 3, false, true, false, AM_ZP }, | 177 | [0x86] = { "STX", STX, 2, 3, false, true, false, false, AM_ZP }, |
| 177 | [0x96] = { "STX", STX, 2, 4, false, true, false, AM_ZP_Y }, | 178 | [0x96] = { "STX", STX, 2, 4, false, true, false, false, AM_ZP_Y }, |
| 178 | [0x8E] = { "STX", STX, 3, 4, false, true, false, AM_ABS }, | 179 | [0x8E] = { "STX", STX, 3, 4, false, true, false, false, AM_ABS }, |
| 179 | [0x84] = { "STY", STY, 2, 3, false, true, false, AM_ZP }, | 180 | [0x84] = { "STY", STY, 2, 3, false, true, false, false, AM_ZP }, |
| 180 | [0x94] = { "STY", STY, 2, 4, false, true, false, AM_ZP_X }, | 181 | [0x94] = { "STY", STY, 2, 4, false, true, false, false, AM_ZP_X }, |
| 181 | [0x8C] = { "STY", STY, 3, 4, false, true, false, AM_ABS }, | 182 | [0x8C] = { "STY", STY, 3, 4, false, true, false, false, AM_ABS }, |
| 182 | [0xAA] = { "TAX", TAX, 1, 2, false, false, false, AM_NONE }, | 183 | [0xAA] = { "TAX", TAX, 1, 2, false, false, false, false, AM_NONE }, |
| 183 | [0xA8] = { "TAY", TAY, 1, 2, false, false, false, AM_NONE }, | 184 | [0xA8] = { "TAY", TAY, 1, 2, false, false, false, false, AM_NONE }, |
| 184 | [0xBA] = { "TSX", TSX, 1, 2, false, false, false, AM_NONE }, | 185 | [0xBA] = { "TSX", TSX, 1, 2, false, false, false, false, AM_NONE }, |
| 185 | [0x8A] = { "TXA", TXA, 1, 2, false, false, false, AM_NONE }, | 186 | [0x8A] = { "TXA", TXA, 1, 2, false, false, false, false, AM_NONE }, |
| 186 | [0x9A] = { "TXS", TXS, 1, 2, false, false, false, AM_NONE }, | 187 | [0x9A] = { "TXS", TXS, 1, 2, false, false, false, false, AM_NONE }, |
| 187 | [0x98] = { "TYA", TYA, 1, 2, false, false, false, AM_NONE }, | 188 | [0x98] = { "TYA", TYA, 1, 2, false, false, false, false, AM_NONE }, |
| 189 | /* unofficial opcodes: https://www.nesdev.org/undocumented_opcodes.txt */ | ||
| 190 | [0x0B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, | ||
| 191 | [0x2B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, | ||
| 192 | [0x87] = { "AAX", AAX, 2, 3, false, false, false, true, AM_ZP }, | ||
| 193 | [0x97] = { "AAX", AAX, 2, 4, false, false, false, true, AM_ZP_Y }, | ||
| 194 | [0x83] = { "AAX", AAX, 2, 6, false, false, false, true, AM_IND_X }, | ||
| 195 | [0x8F] = { "AAX", AAX, 3, 4, false, false, false, true, AM_ABS }, | ||
| 196 | [0x6B] = { "ARR", ARR, 2, 2, false, false, false, true, AM_IMM }, | ||
| 197 | [0x4B] = { "ASR", ASR, 2, 2, false, false, false, true, AM_IMM }, | ||
| 198 | [0xAB] = { "ATX", ATX, 2, 2, false, false, false, true, AM_IMM }, | ||
| 199 | [0x9F] = { "AXA", AXA, 3, 5, false, false, false, true, AM_ABS_Y }, | ||
| 200 | [0x93] = { "AXA", AXA, 2, 6, false, false, false, true, AM_IND_Y }, | ||
| 201 | [0xCB] = { "AXS", AXS, 2, 2, false, false, false, true, AM_IMM }, | ||
| 202 | [0xC7] = { "DCP", DCP, 2, 5, false, false, false, true, AM_ZP }, | ||
| 203 | [0xD7] = { "DCP", DCP, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 204 | [0xCF] = { "DCP", DCP, 3, 6, false, false, false, true, AM_ABS }, | ||
| 205 | [0xDF] = { "DCP", DCP, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 206 | [0xDB] = { "DCP", DCP, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 207 | [0xC3] = { "DCP", DCP, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 208 | [0xD3] = { "DCP", DCP, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 209 | [0x04] = { "NOP", NOP, 2, 3, true, false, false, true, AM_ZP }, | ||
| 210 | [0x14] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | ||
| 211 | [0x34] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | ||
| 212 | [0x44] = { "NOP", NOP, 2, 3, true, false, false, true, AM_ZP }, | ||
| 213 | [0x54] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | ||
| 214 | [0x64] = { "NOP", NOP, 2, 3, true, false, false, true, AM_ZP }, | ||
| 215 | [0x74] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | ||
| 216 | [0x80] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | ||
| 217 | [0x82] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | ||
| 218 | [0x89] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | ||
| 219 | [0xC2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | ||
| 220 | [0xD4] = { "NOP", NOP, 2, 4, false, false, false, true, AM_ZP_X }, | ||
| 221 | [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | ||
| 222 | [0xF4] = { "NOP", NOP, 2, 4, false, false, false, true, AM_ZP_X }, | ||
| 223 | [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, | ||
| 224 | [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 225 | [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, | ||
| 226 | [0xFF] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 227 | [0xFB] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 228 | [0xE3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 229 | [0xF3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 230 | [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 231 | [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 232 | [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 233 | [0x32] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 234 | [0x42] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 235 | [0x52] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 236 | [0x62] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 237 | [0x72] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 238 | [0x92] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 239 | [0xB2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 240 | [0xD2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 241 | [0xF2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | ||
| 242 | [0xBB] = { "LAR", LAR, 3, 4, false, false, true, true, AM_ABS_Y }, | ||
| 243 | [0xA7] = { "LAX", LAX, 2, 3, false, false, false, true, AM_ZP }, | ||
| 244 | [0xB7] = { "LAX", LAX, 2, 4, false, false, false, true, AM_ZP_Y }, | ||
| 245 | [0xAF] = { "LAX", LAX, 3, 4, false, false, false, true, AM_ABS }, | ||
| 246 | [0xBF] = { "LAX", LAX, 3, 4, false, false, true, true, AM_ABS_Y }, | ||
| 247 | [0xA3] = { "LAX", LAX, 2, 6, false, false, false, true, AM_IND_X }, | ||
| 248 | [0xB3] = { "LAX", LAX, 2, 5, false, false, true, true, AM_IND_Y }, | ||
| 249 | [0x1A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 250 | [0x3A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 251 | [0x5A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 252 | [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 253 | [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 254 | [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | ||
| 255 | [0x27] = { "RLA", RLA, 2, 5, false, false, false, true, AM_ZP }, | ||
| 256 | [0x37] = { "RLA", RLA, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 257 | [0x2F] = { "RLA", RLA, 3, 6, false, false, false, true, AM_ABS }, | ||
| 258 | [0x3F] = { "RLA", RLA, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 259 | [0x3B] = { "RLA", RLA, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 260 | [0x23] = { "RLA", RLA, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 261 | [0x33] = { "RLA", RLA, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 262 | [0x67] = { "RRA", RRA, 2, 5, false, false, false, true, AM_ZP }, | ||
| 263 | [0x77] = { "RRA", RRA, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 264 | [0x6F] = { "RRA", RRA, 3, 6, false, false, false, true, AM_ABS }, | ||
| 265 | [0x7F] = { "RRA", RRA, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 266 | [0x7B] = { "RRA", RRA, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 267 | [0x63] = { "RRA", RRA, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 268 | [0x73] = { "RRA", RRA, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 269 | [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, | ||
| 270 | [0x07] = { "SLO", SLO, 2, 5, false, false, false, true, AM_ZP }, | ||
| 271 | [0x17] = { "SLO", SLO, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 272 | [0x0F] = { "SLO", SLO, 3, 6, false, false, false, true, AM_ABS }, | ||
| 273 | [0x1F] = { "SLO", SLO, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 274 | [0x1B] = { "SLO", SLO, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 275 | [0x03] = { "SLO", SLO, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 276 | [0x13] = { "SLO", SLO, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 277 | [0x47] = { "SRE", SRE, 2, 5, false, false, false, true, AM_ZP }, | ||
| 278 | [0x57] = { "SRE", SRE, 2, 6, false, false, false, true, AM_ZP_X }, | ||
| 279 | [0x4F] = { "SRE", SRE, 3, 6, false, false, false, true, AM_ABS }, | ||
| 280 | [0x5F] = { "SRE", SRE, 3, 7, false, false, false, true, AM_ABS_X }, | ||
| 281 | [0x5B] = { "SRE", SRE, 3, 7, false, false, false, true, AM_ABS_Y }, | ||
| 282 | [0x43] = { "SRE", SRE, 2, 8, false, false, false, true, AM_IND_X }, | ||
| 283 | [0x53] = { "SRE", SRE, 2, 8, false, false, false, true, AM_IND_Y }, | ||
| 284 | [0x9E] = { "SXA", SXA, 3, 5, false, false, false, true, AM_ABS_Y }, | ||
| 285 | [0x9C] = { "SYA", SYA, 3, 5, false, false, false, true, AM_ABS_X }, | ||
| 286 | [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, | ||
| 287 | [0x1C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 288 | [0x3C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 289 | [0x5C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 290 | [0x7C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 291 | [0xDC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 292 | [0xFC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | ||
| 293 | [0x8B] = { "XAA", XAA, 2, 2, false, false, false, true, AM_IMM }, | ||
| 294 | [0x9B] = { "XAS", XAS, 3, 5, false, false, false, true, AM_ABS_Y }, | ||
| 188 | }; | 295 | }; |
