diff options
| author | vin <git@vineetk.net> | 2024-07-03 18:52:15 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2024-07-03 19:22:00 -0400 |
| commit | d8bb5a5ccf96fed7e8084cf691c987ce56a8c995 (patch) | |
| tree | 5cfc546f2ae063d1261ef34ee054bd857033231d /opcodes.h | |
| parent | a4b39966aed8d41ad4ddc6700683c4779e8d1cb2 (diff) | |
call opcode function pointer instead of using switch case
Also improve logging.
Diffstat (limited to 'opcodes.h')
| -rw-r--r-- | opcodes.h | 304 |
1 files changed, 153 insertions, 151 deletions
| @@ -1,3 +1,4 @@ | |||
| 1 | #include <stdbool.h> | ||
| 1 | #include <stdint.h> | 2 | #include <stdint.h> |
| 2 | 3 | ||
| 3 | #include "cpu.h" | 4 | #include "cpu.h" |
| @@ -25,160 +26,161 @@ struct opcode { | |||
| 25 | void (*instr)(uint16_t arg); | 26 | void (*instr)(uint16_t arg); |
| 26 | uint8_t bytes; | 27 | uint8_t bytes; |
| 27 | uint8_t cycles; | 28 | uint8_t cycles; |
| 29 | bool didmemory; | ||
| 28 | enum addressing_mode mode; | 30 | enum addressing_mode mode; |
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 31 | struct opcode opcodes[0x100] = { | 33 | struct opcode opcodes[0x100] = { |
| 32 | /* official opcodes */ | 34 | /* official opcodes */ |
| 33 | [0x69] = { "ADC", ADC, 2, 2, AM_IMM }, | 35 | [0x69] = { "ADC", ADC, 2, 2, false, AM_IMM }, |
| 34 | [0x65] = { "ADC", ADC, 2, 3, AM_ZP }, | 36 | [0x65] = { "ADC", ADC, 2, 3, false, AM_ZP }, |
| 35 | [0x75] = { "ADC", ADC, 2, 4, AM_ZP_X }, | 37 | [0x75] = { "ADC", ADC, 2, 4, false, AM_ZP_X }, |
| 36 | [0x6D] = { "ADC", ADC, 3, 4, AM_ABS }, | 38 | [0x6D] = { "ADC", ADC, 3, 4, false, AM_ABS }, |
| 37 | [0x7D] = { "ADC", ADC, 3, 4, AM_ABS_X }, | 39 | [0x7D] = { "ADC", ADC, 3, 4, false, AM_ABS_X }, |
| 38 | [0x79] = { "ADC", ADC, 3, 4, AM_ABS_Y }, | 40 | [0x79] = { "ADC", ADC, 3, 4, false, AM_ABS_Y }, |
| 39 | [0x61] = { "ADC", ADC, 2, 6, AM_IND_X }, | 41 | [0x61] = { "ADC", ADC, 2, 6, false, AM_IND_X }, |
| 40 | [0x71] = { "ADC", ADC, 2, 5, AM_IND_Y }, | 42 | [0x71] = { "ADC", ADC, 2, 5, false, AM_IND_Y }, |
| 41 | [0x29] = { "AND", AND, 2, 2, AM_IMM }, | 43 | [0x29] = { "AND", AND, 2, 2, false, AM_IMM }, |
| 42 | [0x25] = { "AND", AND, 2, 3, AM_ZP }, | 44 | [0x25] = { "AND", AND, 2, 3, false, AM_ZP }, |
| 43 | [0x35] = { "AND", AND, 2, 4, AM_ZP_X }, | 45 | [0x35] = { "AND", AND, 2, 4, false, AM_ZP_X }, |
| 44 | [0x2D] = { "AND", AND, 3, 4, AM_ABS }, | 46 | [0x2D] = { "AND", AND, 3, 4, false, AM_ABS }, |
| 45 | [0x3D] = { "AND", AND, 3, 4, AM_ABS_X }, | 47 | [0x3D] = { "AND", AND, 3, 4, false, AM_ABS_X }, |
| 46 | [0x39] = { "AND", AND, 3, 4, AM_ABS_Y }, | 48 | [0x39] = { "AND", AND, 3, 4, false, AM_ABS_Y }, |
| 47 | [0x21] = { "AND", AND, 2, 6, AM_IND_X }, | 49 | [0x21] = { "AND", AND, 2, 6, false, AM_IND_X }, |
| 48 | [0x31] = { "AND", AND, 2, 5, AM_IND_Y }, | 50 | [0x31] = { "AND", AND, 2, 5, false, AM_IND_Y }, |
| 49 | [0x0A] = { "ASL", ASL_acc, 1, 2, AM_ACC }, | 51 | [0x0A] = { "ASL", ASL_acc, 1, 2, false, AM_ACC }, |
| 50 | [0x06] = { "ASL", ASL, 2, 5, AM_ZP }, | 52 | [0x06] = { "ASL", ASL, 2, 5, true, AM_ZP }, |
| 51 | [0x16] = { "ASL", ASL, 2, 6, AM_ZP_X }, | 53 | [0x16] = { "ASL", ASL, 2, 6, true, AM_ZP_X }, |
| 52 | [0x0E] = { "ASL", ASL, 3, 6, AM_ABS }, | 54 | [0x0E] = { "ASL", ASL, 3, 6, true, AM_ABS }, |
| 53 | [0x1E] = { "ASL", ASL, 3, 7, AM_ABS_X }, | 55 | [0x1E] = { "ASL", ASL, 3, 7, true, AM_ABS_X }, |
| 54 | [0x90] = { "BCC", BCC, 2, 2, AM_REL }, | 56 | [0x90] = { "BCC", BCC, 2, 2, false, AM_REL }, |
| 55 | [0xB0] = { "BCS", BCS, 2, 2, AM_REL }, | 57 | [0xB0] = { "BCS", BCS, 2, 2, false, AM_REL }, |
| 56 | [0xF0] = { "BEQ", BEQ, 2, 2, AM_REL }, | 58 | [0xF0] = { "BEQ", BEQ, 2, 2, false, AM_REL }, |
| 57 | [0x24] = { "BIT", BIT, 2, 3, AM_ZP }, | 59 | [0x24] = { "BIT", BIT, 2, 3, true, AM_ZP }, |
| 58 | [0x2C] = { "BIT", BIT, 3, 4, AM_ABS }, | 60 | [0x2C] = { "BIT", BIT, 3, 4, true, AM_ABS }, |
| 59 | [0x30] = { "BMI", BMI, 2, 2, AM_REL }, | 61 | [0x30] = { "BMI", BMI, 2, 2, false, AM_REL }, |
| 60 | [0xD0] = { "BNE", BNE, 2, 2, AM_REL }, | 62 | [0xD0] = { "BNE", BNE, 2, 2, false, AM_REL }, |
| 61 | [0x10] = { "BPL", BPL, 2, 2, AM_REL }, | 63 | [0x10] = { "BPL", BPL, 2, 2, false, AM_REL }, |
| 62 | [0x00] = { "BRK", BRK, 1, 7, AM_NONE }, | 64 | [0x00] = { "BRK", BRK, 1, 7, false, AM_NONE }, |
| 63 | [0x50] = { "BVC", BVC, 2, 2, AM_REL }, | 65 | [0x50] = { "BVC", BVC, 2, 2, false, AM_REL }, |
| 64 | [0x70] = { "BVS", BVS, 2, 2, AM_REL }, | 66 | [0x70] = { "BVS", BVS, 2, 2, false, AM_REL }, |
| 65 | [0x18] = { "CLC", CLC, 1, 2, AM_NONE }, | 67 | [0x18] = { "CLC", CLC, 1, 2, false, AM_NONE }, |
| 66 | [0xD8] = { "CLD", CLD, 1, 2, AM_NONE }, | 68 | [0xD8] = { "CLD", CLD, 1, 2, false, AM_NONE }, |
| 67 | [0x58] = { "CLI", CLI, 1, 2, AM_NONE }, | 69 | [0x58] = { "CLI", CLI, 1, 2, false, AM_NONE }, |
| 68 | [0xB8] = { "CLV", CLV, 1, 2, AM_NONE }, | 70 | [0xB8] = { "CLV", CLV, 1, 2, false, AM_NONE }, |
| 69 | [0xC9] = { "CMP", CMP, 2, 2, AM_IMM }, | 71 | [0xC9] = { "CMP", CMP, 2, 2, false, AM_IMM }, |
| 70 | [0xC5] = { "CMP", CMP, 2, 3, AM_ZP }, | 72 | [0xC5] = { "CMP", CMP, 2, 3, false, AM_ZP }, |
| 71 | [0xD5] = { "CMP", CMP, 2, 4, AM_ZP_X }, | 73 | [0xD5] = { "CMP", CMP, 2, 4, false, AM_ZP_X }, |
| 72 | [0xCD] = { "CMP", CMP, 3, 4, AM_ABS }, | 74 | [0xCD] = { "CMP", CMP, 3, 4, false, AM_ABS }, |
| 73 | [0xDD] = { "CMP", CMP, 3, 4, AM_ABS_X }, | 75 | [0xDD] = { "CMP", CMP, 3, 4, false, AM_ABS_X }, |
| 74 | [0xD9] = { "CMP", CMP, 3, 4, AM_ABS_Y }, | 76 | [0xD9] = { "CMP", CMP, 3, 4, false, AM_ABS_Y }, |
| 75 | [0xC1] = { "CMP", CMP, 2, 6, AM_IND_X }, | 77 | [0xC1] = { "CMP", CMP, 2, 6, false, AM_IND_X }, |
| 76 | [0xD1] = { "CMP", CMP, 2, 5, AM_IND_Y }, | 78 | [0xD1] = { "CMP", CMP, 2, 5, false, AM_IND_Y }, |
| 77 | [0xE0] = { "CPX", CPX, 2, 2, AM_IMM }, | 79 | [0xE0] = { "CPX", CPX, 2, 2, false, AM_IMM }, |
| 78 | [0xE4] = { "CPX", CPX, 2, 3, AM_ZP }, | 80 | [0xE4] = { "CPX", CPX, 2, 3, false, AM_ZP }, |
| 79 | [0xEC] = { "CPX", CPX, 3, 4, AM_ABS }, | 81 | [0xEC] = { "CPX", CPX, 3, 4, false, AM_ABS }, |
| 80 | [0xC0] = { "CPY", CPY, 2, 2, AM_IMM }, | 82 | [0xC0] = { "CPY", CPY, 2, 2, false, AM_IMM }, |
| 81 | [0xC4] = { "CPY", CPY, 2, 3, AM_ZP }, | 83 | [0xC4] = { "CPY", CPY, 2, 3, false, AM_ZP }, |
| 82 | [0xCC] = { "CPY", CPY, 3, 4, AM_ABS }, | 84 | [0xCC] = { "CPY", CPY, 3, 4, false, AM_ABS }, |
| 83 | [0xC6] = { "DEC", DEC, 2, 5, AM_ZP }, | 85 | [0xC6] = { "DEC", DEC, 2, 5, true, AM_ZP }, |
| 84 | [0xD6] = { "DEC", DEC, 2, 6, AM_ZP_X }, | 86 | [0xD6] = { "DEC", DEC, 2, 6, true, AM_ZP_X }, |
| 85 | [0xCE] = { "DEC", DEC, 3, 6, AM_ABS }, | 87 | [0xCE] = { "DEC", DEC, 3, 6, true, AM_ABS }, |
| 86 | [0xDE] = { "DEC", DEC, 3, 7, AM_ABS_X }, | 88 | [0xDE] = { "DEC", DEC, 3, 7, true, AM_ABS_X }, |
| 87 | [0xCA] = { "DEX", DEX, 1, 2, AM_NONE }, | 89 | [0xCA] = { "DEX", DEX, 1, 2, false, AM_NONE }, |
| 88 | [0x88] = { "DEY", DEY, 1, 2, AM_NONE }, | 90 | [0x88] = { "DEY", DEY, 1, 2, false, AM_NONE }, |
| 89 | [0x49] = { "EOR", EOR, 2, 2, AM_IMM }, | 91 | [0x49] = { "EOR", EOR, 2, 2, false, AM_IMM }, |
| 90 | [0x45] = { "EOR", EOR, 2, 3, AM_ZP }, | 92 | [0x45] = { "EOR", EOR, 2, 3, false, AM_ZP }, |
| 91 | [0x55] = { "EOR", EOR, 2, 4, AM_ZP_X }, | 93 | [0x55] = { "EOR", EOR, 2, 4, false, AM_ZP_X }, |
| 92 | [0x4D] = { "EOR", EOR, 3, 4, AM_ABS }, | 94 | [0x4D] = { "EOR", EOR, 3, 4, false, AM_ABS }, |
| 93 | [0x5D] = { "EOR", EOR, 3, 4, AM_ABS_X }, | 95 | [0x5D] = { "EOR", EOR, 3, 4, false, AM_ABS_X }, |
| 94 | [0x59] = { "EOR", EOR, 3, 4, AM_ABS_Y }, | 96 | [0x59] = { "EOR", EOR, 3, 4, false, AM_ABS_Y }, |
| 95 | [0x41] = { "EOR", EOR, 2, 6, AM_IND_X }, | 97 | [0x41] = { "EOR", EOR, 2, 6, false, AM_IND_X }, |
| 96 | [0x51] = { "EOR", EOR, 2, 5, AM_IND_Y }, | 98 | [0x51] = { "EOR", EOR, 2, 5, false, AM_IND_Y }, |
| 97 | [0xE6] = { "INC", INC, 2, 5, AM_ZP }, | 99 | [0xE6] = { "INC", INC, 2, 5, true, AM_ZP }, |
| 98 | [0xF6] = { "INC", INC, 2, 6, AM_ZP_X }, | 100 | [0xF6] = { "INC", INC, 2, 6, true, AM_ZP_X }, |
| 99 | [0xEE] = { "INC", INC, 3, 6, AM_ABS }, | 101 | [0xEE] = { "INC", INC, 3, 6, true, AM_ABS }, |
| 100 | [0xFE] = { "INC", INC, 3, 7, AM_ABS_X }, | 102 | [0xFE] = { "INC", INC, 3, 7, true, AM_ABS_X }, |
| 101 | [0xE8] = { "INX", INX, 1, 2, AM_NONE }, | 103 | [0xE8] = { "INX", INX, 1, 2, false, AM_NONE }, |
| 102 | [0xC8] = { "INY", INY, 1, 2, AM_NONE }, | 104 | [0xC8] = { "INY", INY, 1, 2, false, AM_NONE }, |
| 103 | [0x4C] = { "JMP", JMP, 3, 3, AM_ABS }, | 105 | [0x4C] = { "JMP", JMP, 3, 3, false, AM_ABS }, |
| 104 | [0x6C] = { "JMP", JMP, 3, 5, AM_IND }, | 106 | [0x6C] = { "JMP", JMP, 3, 5, false, AM_IND }, |
| 105 | [0x20] = { "JSR", JSR, 3, 6, AM_ABS }, | 107 | [0x20] = { "JSR", JSR, 3, 6, false, AM_ABS }, |
| 106 | [0xA9] = { "LDA", LDA, 2, 2, AM_IMM }, | 108 | [0xA9] = { "LDA", LDA, 2, 2, false, AM_IMM }, |
| 107 | [0xA5] = { "LDA", LDA, 2, 3, AM_ZP }, | 109 | [0xA5] = { "LDA", LDA, 2, 3, false, AM_ZP }, |
| 108 | [0xB5] = { "LDA", LDA, 2, 4, AM_ZP_X }, | 110 | [0xB5] = { "LDA", LDA, 2, 4, false, AM_ZP_X }, |
| 109 | [0xAD] = { "LDA", LDA, 3, 4, AM_ABS }, | 111 | [0xAD] = { "LDA", LDA, 3, 4, false, AM_ABS }, |
| 110 | [0xBD] = { "LDA", LDA, 3, 4, AM_ABS_X }, | 112 | [0xBD] = { "LDA", LDA, 3, 4, false, AM_ABS_X }, |
| 111 | [0xB9] = { "LDA", LDA, 3, 4, AM_ABS_Y }, | 113 | [0xB9] = { "LDA", LDA, 3, 4, false, AM_ABS_Y }, |
| 112 | [0xA1] = { "LDA", LDA, 2, 6, AM_IND_X }, | 114 | [0xA1] = { "LDA", LDA, 2, 6, false, AM_IND_X }, |
| 113 | [0xB1] = { "LDA", LDA, 2, 5, AM_IND_Y }, | 115 | [0xB1] = { "LDA", LDA, 2, 5, false, AM_IND_Y }, |
| 114 | [0xA2] = { "LDX", LDX, 2, 2, AM_IMM }, | 116 | [0xA2] = { "LDX", LDX, 2, 2, false, AM_IMM }, |
| 115 | [0xA6] = { "LDX", LDX, 2, 3, AM_ZP }, | 117 | [0xA6] = { "LDX", LDX, 2, 3, true, AM_ZP }, |
| 116 | [0xB6] = { "LDX", LDX, 2, 4, AM_ZP_Y }, | 118 | [0xB6] = { "LDX", LDX, 2, 4, false, AM_ZP_Y }, |
| 117 | [0xAE] = { "LDX", LDX, 3, 4, AM_ABS }, | 119 | [0xAE] = { "LDX", LDX, 3, 4, true, AM_ABS }, |
| 118 | [0xBE] = { "LDX", LDX, 3, 4, AM_ABS_Y }, | 120 | [0xBE] = { "LDX", LDX, 3, 4, false, AM_ABS_Y }, |
| 119 | [0xA0] = { "LDY", LDY, 2, 2, AM_IMM }, | 121 | [0xA0] = { "LDY", LDY, 2, 2, false, AM_IMM }, |
| 120 | [0xA4] = { "LDY", LDY, 2, 3, AM_ZP }, | 122 | [0xA4] = { "LDY", LDY, 2, 3, false, AM_ZP }, |
| 121 | [0xB4] = { "LDY", LDY, 2, 4, AM_ZP_X }, | 123 | [0xB4] = { "LDY", LDY, 2, 4, false, AM_ZP_X }, |
| 122 | [0xAC] = { "LDY", LDY, 3, 4, AM_ABS }, | 124 | [0xAC] = { "LDY", LDY, 3, 4, false, AM_ABS }, |
| 123 | [0xBC] = { "LDY", LDY, 3, 4, AM_ABS_X }, | 125 | [0xBC] = { "LDY", LDY, 3, 4, false, AM_ABS_X }, |
| 124 | [0x4A] = { "LSR", LSR_acc, 1, 2, AM_ACC }, | 126 | [0x4A] = { "LSR", LSR_acc, 1, 2, false, AM_ACC }, |
| 125 | [0x46] = { "LSR", LSR, 2, 5, AM_ZP }, | 127 | [0x46] = { "LSR", LSR, 2, 5, true, AM_ZP }, |
| 126 | [0x56] = { "LSR", LSR, 2, 6, AM_ZP_X }, | 128 | [0x56] = { "LSR", LSR, 2, 6, true, AM_ZP_X }, |
| 127 | [0x4E] = { "LSR", LSR, 3, 6, AM_ABS }, | 129 | [0x4E] = { "LSR", LSR, 3, 6, true, AM_ABS }, |
| 128 | [0x5E] = { "LSR", LSR, 3, 7, AM_ABS_X }, | 130 | [0x5E] = { "LSR", LSR, 3, 7, true, AM_ABS_X }, |
| 129 | [0xEA] = { "NOP", NOP, 1, 2, AM_NONE }, | 131 | [0xEA] = { "NOP", NOP, 1, 2, false, AM_NONE }, |
| 130 | [0x09] = { "ORA", ORA, 2, 2, AM_IMM }, | 132 | [0x09] = { "ORA", ORA, 2, 2, false, AM_IMM }, |
| 131 | [0x05] = { "ORA", ORA, 2, 3, AM_ZP }, | 133 | [0x05] = { "ORA", ORA, 2, 3, false, AM_ZP }, |
| 132 | [0x15] = { "ORA", ORA, 2, 4, AM_ZP_X }, | 134 | [0x15] = { "ORA", ORA, 2, 4, false, AM_ZP_X }, |
| 133 | [0x0D] = { "ORA", ORA, 3, 4, AM_ABS }, | 135 | [0x0D] = { "ORA", ORA, 3, 4, false, AM_ABS }, |
| 134 | [0x1D] = { "ORA", ORA, 3, 4, AM_ABS_X }, | 136 | [0x1D] = { "ORA", ORA, 3, 4, false, AM_ABS_X }, |
| 135 | [0x19] = { "ORA", ORA, 3, 4, AM_ABS_Y }, | 137 | [0x19] = { "ORA", ORA, 3, 4, false, AM_ABS_Y }, |
| 136 | [0x01] = { "ORA", ORA, 2, 6, AM_IND_X }, | 138 | [0x01] = { "ORA", ORA, 2, 6, false, AM_IND_X }, |
| 137 | [0x11] = { "ORA", ORA, 2, 5, AM_IND_Y }, | 139 | [0x11] = { "ORA", ORA, 2, 5, false, AM_IND_Y }, |
| 138 | [0x48] = { "PHA", PHA, 1, 3, AM_NONE }, | 140 | [0x48] = { "PHA", PHA, 1, 3, false, AM_NONE }, |
| 139 | [0x08] = { "PHP", PHP, 1, 3, AM_NONE }, | 141 | [0x08] = { "PHP", PHP, 1, 3, false, AM_NONE }, |
| 140 | [0x68] = { "PLA", PLA, 1, 4, AM_NONE }, | 142 | [0x68] = { "PLA", PLA, 1, 4, false, AM_NONE }, |
| 141 | [0x28] = { "PLP", PLP, 1, 4, AM_NONE }, | 143 | [0x28] = { "PLP", PLP, 1, 4, false, AM_NONE }, |
| 142 | [0x2A] = { "ROL", ROL_acc, 1, 2, AM_ACC }, | 144 | [0x2A] = { "ROL", ROL_acc, 1, 2, false, AM_ACC }, |
| 143 | [0x26] = { "ROL", ROL, 2, 5, AM_ZP }, | 145 | [0x26] = { "ROL", ROL, 2, 5, true, AM_ZP }, |
| 144 | [0x36] = { "ROL", ROL, 2, 6, AM_ZP_X }, | 146 | [0x36] = { "ROL", ROL, 2, 6, true, AM_ZP_X }, |
| 145 | [0x2E] = { "ROL", ROL, 3, 6, AM_ABS }, | 147 | [0x2E] = { "ROL", ROL, 3, 6, true, AM_ABS }, |
| 146 | [0x3E] = { "ROL", ROL, 3, 7, AM_ABS_X }, | 148 | [0x3E] = { "ROL", ROL, 3, 7, true, AM_ABS_X }, |
| 147 | [0x6A] = { "ROR", ROR_acc, 1, 2, AM_ACC }, | 149 | [0x6A] = { "ROR", ROR_acc, 1, 2, false, AM_ACC }, |
| 148 | [0x66] = { "ROR", ROR, 2, 5, AM_ZP }, | 150 | [0x66] = { "ROR", ROR, 2, 5, true, AM_ZP }, |
| 149 | [0x76] = { "ROR", ROR, 2, 6, AM_ZP_X }, | 151 | [0x76] = { "ROR", ROR, 2, 6, true, AM_ZP_X }, |
| 150 | [0x6E] = { "ROR", ROR, 3, 6, AM_ABS }, | 152 | [0x6E] = { "ROR", ROR, 3, 6, true, AM_ABS }, |
| 151 | [0x7E] = { "ROR", ROR, 3, 7, AM_ABS_X }, | 153 | [0x7E] = { "ROR", ROR, 3, 7, true, AM_ABS_X }, |
| 152 | [0x40] = { "RTI", RTI, 1, 6, AM_NONE }, | 154 | [0x40] = { "RTI", RTI, 1, 6, false, AM_NONE }, |
| 153 | [0x60] = { "RTS", RTS, 1, 6, AM_NONE }, | 155 | [0x60] = { "RTS", RTS, 1, 6, false, AM_NONE }, |
| 154 | [0xE9] = { "SBC", SBC, 2, 2, AM_IMM }, | 156 | [0xE9] = { "SBC", SBC, 2, 2, false, AM_IMM }, |
| 155 | [0xE5] = { "SBC", SBC, 2, 3, AM_ZP }, | 157 | [0xE5] = { "SBC", SBC, 2, 3, false, AM_ZP }, |
| 156 | [0xF5] = { "SBC", SBC, 2, 4, AM_ZP_X }, | 158 | [0xF5] = { "SBC", SBC, 2, 4, false, AM_ZP_X }, |
| 157 | [0xED] = { "SBC", SBC, 3, 4, AM_ABS }, | 159 | [0xED] = { "SBC", SBC, 3, 4, false, AM_ABS }, |
| 158 | [0xFD] = { "SBC", SBC, 3, 4, AM_ABS_X }, | 160 | [0xFD] = { "SBC", SBC, 3, 4, false, AM_ABS_X }, |
| 159 | [0xF9] = { "SBC", SBC, 3, 4, AM_ABS_Y }, | 161 | [0xF9] = { "SBC", SBC, 3, 4, false, AM_ABS_Y }, |
| 160 | [0xE1] = { "SBC", SBC, 2, 6, AM_IND_X }, | 162 | [0xE1] = { "SBC", SBC, 2, 6, false, AM_IND_X }, |
| 161 | [0xF1] = { "SBC", SBC, 2, 5, AM_IND_Y }, | 163 | [0xF1] = { "SBC", SBC, 2, 5, false, AM_IND_Y }, |
| 162 | [0x38] = { "SEC", SEC, 1, 2, AM_NONE }, | 164 | [0x38] = { "SEC", SEC, 1, 2, false, AM_NONE }, |
| 163 | [0xF8] = { "SED", SED, 1, 2, AM_NONE }, | 165 | [0xF8] = { "SED", SED, 1, 2, false, AM_NONE }, |
| 164 | [0x78] = { "SEI", SEI, 1, 2, AM_NONE }, | 166 | [0x78] = { "SEI", SEI, 1, 2, false, AM_NONE }, |
| 165 | [0x85] = { "STA", STA, 2, 3, AM_ZP }, | 167 | [0x85] = { "STA", STA, 2, 3, true, AM_ZP }, |
| 166 | [0x95] = { "STA", STA, 2, 4, AM_ZP_X }, | 168 | [0x95] = { "STA", STA, 2, 4, true, AM_ZP_X }, |
| 167 | [0x8D] = { "STA", STA, 3, 4, AM_ABS }, | 169 | [0x8D] = { "STA", STA, 3, 4, true, AM_ABS }, |
| 168 | [0x9D] = { "STA", STA, 3, 5, AM_ABS_X }, | 170 | [0x9D] = { "STA", STA, 3, 5, true, AM_ABS_X }, |
| 169 | [0x99] = { "STA", STA, 3, 5, AM_ABS_Y }, | 171 | [0x99] = { "STA", STA, 3, 5, true, AM_ABS_Y }, |
| 170 | [0x81] = { "STA", STA, 2, 6, AM_IND_X }, | 172 | [0x81] = { "STA", STA, 2, 6, true, AM_IND_X }, |
| 171 | [0x91] = { "STA", STA, 2, 6, AM_IND_Y }, | 173 | [0x91] = { "STA", STA, 2, 6, true, AM_IND_Y }, |
| 172 | [0x86] = { "STX", STX, 2, 3, AM_ZP }, | 174 | [0x86] = { "STX", STX, 2, 3, true, AM_ZP }, |
| 173 | [0x96] = { "STX", STX, 2, 4, AM_ZP_Y }, | 175 | [0x96] = { "STX", STX, 2, 4, true, AM_ZP_Y }, |
| 174 | [0x8E] = { "STX", STX, 3, 4, AM_ABS }, | 176 | [0x8E] = { "STX", STX, 3, 4, true, AM_ABS }, |
| 175 | [0x84] = { "STY", STY, 2, 3, AM_ZP }, | 177 | [0x84] = { "STY", STY, 2, 3, true, AM_ZP }, |
| 176 | [0x94] = { "STY", STY, 2, 4, AM_ZP_X }, | 178 | [0x94] = { "STY", STY, 2, 4, true, AM_ZP_X }, |
| 177 | [0x8C] = { "STY", STY, 3, 4, AM_ABS }, | 179 | [0x8C] = { "STY", STY, 3, 4, true, AM_ABS }, |
| 178 | [0xAA] = { "TAX", TAX, 1, 2, AM_NONE }, | 180 | [0xAA] = { "TAX", TAX, 1, 2, false, AM_NONE }, |
| 179 | [0xA8] = { "TAY", TAY, 1, 2, AM_NONE }, | 181 | [0xA8] = { "TAY", TAY, 1, 2, false, AM_NONE }, |
| 180 | [0xBA] = { "TSX", TSX, 1, 2, AM_NONE }, | 182 | [0xBA] = { "TSX", TSX, 1, 2, false, AM_NONE }, |
| 181 | [0x8A] = { "TXA", TXA, 1, 2, AM_NONE }, | 183 | [0x8A] = { "TXA", TXA, 1, 2, false, AM_NONE }, |
| 182 | [0x9A] = { "TXS", TXS, 1, 2, AM_NONE }, | 184 | [0x9A] = { "TXS", TXS, 1, 2, false, AM_NONE }, |
| 183 | [0x98] = { "TYA", TYA, 1, 2, AM_NONE }, | 185 | [0x98] = { "TYA", TYA, 1, 2, false, AM_NONE }, |
| 184 | }; | 186 | }; |
