diff options
| author | vin <git@vineetk.net> | 2024-07-04 15:06:15 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2024-07-04 15:06:15 -0400 |
| commit | e1cdd7386807050bdd7db7debb902425a78e2970 (patch) | |
| tree | d304c8a346d8ca991c83525cf9c3a0814469791d /opcodes.h | |
| parent | 4ccf9f5cee97c8c2191660a5632ab2da60757f97 (diff) | |
implement all of the nestest unofficial opcodes and fix branch cycles
Diffstat (limited to 'opcodes.h')
| -rw-r--r-- | opcodes.h | 70 |
1 files changed, 35 insertions, 35 deletions
| @@ -220,13 +220,13 @@ struct opcode opcodes[0x100] = { | |||
| 220 | [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | 220 | [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| 221 | [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | 221 | [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, |
| 222 | [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | 222 | [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| 223 | [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, | 223 | [0xE7] = { "ISB", ISB, 2, 5, false, true, false, true, AM_ZP }, |
| 224 | [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, | 224 | [0xF7] = { "ISB", ISB, 2, 6, false, true, false, true, AM_ZP_X }, |
| 225 | [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, | 225 | [0xEF] = { "ISB", ISB, 3, 6, false, true, false, true, AM_ABS }, |
| 226 | [0xFF] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_X }, | 226 | [0xFF] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_X }, |
| 227 | [0xFB] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_Y }, | 227 | [0xFB] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 228 | [0xE3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_X }, | 228 | [0xE3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_X }, |
| 229 | [0xF3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_Y }, | 229 | [0xF3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_Y }, |
| 230 | [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 230 | [0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| 231 | [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 231 | [0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| 232 | [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 232 | [0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| @@ -252,35 +252,35 @@ struct opcode opcodes[0x100] = { | |||
| 252 | [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 252 | [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 253 | [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 253 | [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 254 | [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 254 | [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 255 | [0x27] = { "RLA", RLA, 2, 5, true, true, false, true, AM_ZP }, | 255 | [0x27] = { "RLA", RLA, 2, 5, false, true, false, true, AM_ZP }, |
| 256 | [0x37] = { "RLA", RLA, 2, 6, true, true, false, true, AM_ZP_X }, | 256 | [0x37] = { "RLA", RLA, 2, 6, false, true, false, true, AM_ZP_X }, |
| 257 | [0x2F] = { "RLA", RLA, 3, 6, true, true, false, true, AM_ABS }, | 257 | [0x2F] = { "RLA", RLA, 3, 6, false, true, false, true, AM_ABS }, |
| 258 | [0x3F] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_X }, | 258 | [0x3F] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_X }, |
| 259 | [0x3B] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_Y }, | 259 | [0x3B] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 260 | [0x23] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_X }, | 260 | [0x23] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_X }, |
| 261 | [0x33] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_Y }, | 261 | [0x33] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_Y }, |
| 262 | [0x67] = { "RRA", RRA, 2, 5, true, true, false, true, AM_ZP }, | 262 | [0x67] = { "RRA", RRA, 2, 5, false, true, false, true, AM_ZP }, |
| 263 | [0x77] = { "RRA", RRA, 2, 6, true, true, false, true, AM_ZP_X }, | 263 | [0x77] = { "RRA", RRA, 2, 6, false, true, false, true, AM_ZP_X }, |
| 264 | [0x6F] = { "RRA", RRA, 3, 6, true, true, false, true, AM_ABS }, | 264 | [0x6F] = { "RRA", RRA, 3, 6, false, true, false, true, AM_ABS }, |
| 265 | [0x7F] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_X }, | 265 | [0x7F] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_X }, |
| 266 | [0x7B] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_Y }, | 266 | [0x7B] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 267 | [0x63] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_X }, | 267 | [0x63] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_X }, |
| 268 | [0x73] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_Y }, | 268 | [0x73] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_Y }, |
| 269 | [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, | 269 | [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, |
| 270 | [0x07] = { "SLO", SLO, 2, 5, true, true, false, true, AM_ZP }, | 270 | [0x07] = { "SLO", SLO, 2, 5, false, true, false, true, AM_ZP }, |
| 271 | [0x17] = { "SLO", SLO, 2, 6, true, true, false, true, AM_ZP_X }, | 271 | [0x17] = { "SLO", SLO, 2, 6, false, true, false, true, AM_ZP_X }, |
| 272 | [0x0F] = { "SLO", SLO, 3, 6, true, true, false, true, AM_ABS }, | 272 | [0x0F] = { "SLO", SLO, 3, 6, false, true, false, true, AM_ABS }, |
| 273 | [0x1F] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_X }, | 273 | [0x1F] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_X }, |
| 274 | [0x1B] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_Y }, | 274 | [0x1B] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 275 | [0x03] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_X }, | 275 | [0x03] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_X }, |
| 276 | [0x13] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_Y }, | 276 | [0x13] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_Y }, |
| 277 | [0x47] = { "SRE", SRE, 2, 5, true, true, false, true, AM_ZP }, | 277 | [0x47] = { "SRE", SRE, 2, 5, false, true, false, true, AM_ZP }, |
| 278 | [0x57] = { "SRE", SRE, 2, 6, true, true, false, true, AM_ZP_X }, | 278 | [0x57] = { "SRE", SRE, 2, 6, false, true, false, true, AM_ZP_X }, |
| 279 | [0x4F] = { "SRE", SRE, 3, 6, true, true, false, true, AM_ABS }, | 279 | [0x4F] = { "SRE", SRE, 3, 6, false, true, false, true, AM_ABS }, |
| 280 | [0x5F] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_X }, | 280 | [0x5F] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_X }, |
| 281 | [0x5B] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_Y }, | 281 | [0x5B] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 282 | [0x43] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_X }, | 282 | [0x43] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_X }, |
| 283 | [0x53] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_Y }, | 283 | [0x53] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_Y }, |
| 284 | [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y }, | 284 | [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y }, |
| 285 | [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X }, | 285 | [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X }, |
| 286 | [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, | 286 | [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, |
