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-rw-r--r--cpu.c89
-rw-r--r--opcodes.h305
2 files changed, 182 insertions, 212 deletions
diff --git a/cpu.c b/cpu.c
index 6e44c7f..df9c852 100644
--- a/cpu.c
+++ b/cpu.c
@@ -99,55 +99,6 @@ memwrite16(uint16_t addr, uint16_t word)
99 memory[addr + 1] = (word & 0xFF00) >> 8; 99 memory[addr + 1] = (word & 0xFF00) >> 8;
100} 100}
101 101
102static uint8_t
103opcode_arg(enum addressing_mode mode)
104{
105 uint16_t arg, val;
106
107 if (mode != AM_ABS && mode != AM_ABS_X && mode != AM_ABS_Y) {
108 arg = peek(regs.pc++);
109 } else {
110 arg = peek16(regs.pc);
111 regs.pc += 2;
112 }
113
114 switch (mode) {
115 case AM_IMM:
116 case AM_REL:
117 val = arg;
118 break;
119 case AM_ZP:
120 val = peek(arg % 256);
121 break;
122 case AM_ZP_X:
123 val = peek((arg + regs.x) % 256);
124 break;
125 case AM_ZP_Y:
126 val = peek((arg + regs.y) % 256);
127 break;
128 case AM_ABS:
129 val = peek16(arg);
130 break;
131 case AM_ABS_X:
132 val = peek16(arg + regs.x);
133 break;
134 case AM_ABS_Y:
135 val = peek16(arg + regs.y);
136 break;
137 case AM_IND_X:
138 val = peek(peek((arg + regs.x) % 256) + peek((arg + regs.x + 1) % 256) * 256);
139 break;
140 case AM_IND_Y:
141 val = peek(peek(arg) + peek((arg + 1) % 256) * 256 + regs.y);
142 break;
143 default:
144 fprintf(stderr, "INVALID ADDRESSING MODE %i\n", mode);
145 abort();
146 }
147
148 return val;
149}
150
151static uint16_t 102static uint16_t
152opcode_mem(enum addressing_mode mode) 103opcode_mem(enum addressing_mode mode)
153{ 104{
@@ -193,7 +144,7 @@ opcode_mem(enum addressing_mode mode)
193 val = peek(arg) + peek((arg + 1) % 256) * 256 + regs.y; 144 val = peek(arg) + peek((arg + 1) % 256) * 256 + regs.y;
194 break; 145 break;
195 default: 146 default:
196 fprintf(stderr, "opcode_mem INVALID ADDRESSING MODE %i\n", mode); 147 fprintf(stderr, "INVALID ADDRESSING MODE %i\n", mode);
197 abort(); 148 abort();
198 } 149 }
199 150
@@ -271,7 +222,8 @@ BEQ(uint16_t arg)
271void 222void
272BIT(uint16_t arg) 223BIT(uint16_t arg)
273{ 224{
274 uint8_t tmp = peek(arg); 225 uint8_t tmp = arg;
226
275 regs.status.zero = (regs.a & tmp) == 0; 227 regs.status.zero = (regs.a & tmp) == 0;
276 regs.status.overflow = (tmp & (1 << 6)) != 0; 228 regs.status.overflow = (tmp & (1 << 6)) != 0;
277 STATUS_UPDATE_NEGATIVE(tmp); 229 STATUS_UPDATE_NEGATIVE(tmp);
@@ -628,8 +580,18 @@ RTS(uint16_t arg)
628void 580void
629SBC(uint16_t arg) 581SBC(uint16_t arg)
630{ 582{
631 /* SBC is described online as ADC with argument as two's complement */ 583 uint8_t tmp = arg & 0xFF;
632 ADC(~(uint8_t)arg); 584 uint16_t diff;
585
586 diff = regs.a - tmp - !regs.status.carry;
587
588 regs.status.carry = diff > 0xFF;
589 regs.status.carry = !regs.status.carry;
590 /* overflow flag formula: https://stackoverflow.com/a/29224684 */
591 regs.status.overflow = ((regs.a ^ arg) & (regs.a ^ diff) & 0x80) != 0;
592 regs.a = diff & 0xFF;
593
594 STATUS_UPDATE_NZ(regs.a);
633} 595}
634 596
635void 597void
@@ -759,10 +721,10 @@ interpret(void)
759 printf("$%04X", arg); 721 printf("$%04X", arg);
760 break; 722 break;
761 case AM_ABS_X: 723 case AM_ABS_X:
762 printf("$%04X,X", arg); 724 printf("$%04X,X @ %04X", arg - regs.x, arg);
763 break; 725 break;
764 case AM_ABS_Y: 726 case AM_ABS_Y:
765 printf("$%04X,Y", arg); 727 printf("$%04X,Y @ %04X", arg - regs.y, arg);
766 break; 728 break;
767 case AM_IND: 729 case AM_IND:
768 printf("($%04X) = %04X\t\t", arg, peek16(arg)); 730 printf("($%04X) = %04X\t\t", arg, peek16(arg));
@@ -776,13 +738,20 @@ interpret(void)
776 break; 738 break;
777 } 739 }
778 740
779 if (opcodes[op].didmemory) printf(" = %02X", peek(arg)); 741 if (opcodes[op].memread || opcodes[op].memwrite)
780 printf("\t\t\t"); 742 printf(" = %02X", peek(arg));
743
744 if (mode != AM_ABS_X && mode != AM_ABS_Y)
745 putchar('\t');
746 printf("\t\t");
781 747
782 printf("A:%02X X:%02X Y:%02X P:%02X SP:%02X CYC:%d %08b\n", 748 printf("A:%02X X:%02X Y:%02X P:%02X SP:%02X CYC:%d\n",
783 regs.a, regs.x, regs.y, STATUS_TO_INT(), regs.sp, cycles, STATUS_TO_INT()); 749 regs.a, regs.x, regs.y, STATUS_TO_INT(), regs.sp, cycles);
784 750
785 opcodes[op].instr(arg); 751 if (opcodes[op].memread)
752 opcodes[op].instr(peek(arg));
753 else
754 opcodes[op].instr(arg);
786 cycles += opcodes[op].cycles; 755 cycles += opcodes[op].cycles;
787 } 756 }
788loop_exit: 757loop_exit:
diff --git a/opcodes.h b/opcodes.h
index ef57ab0..02b30e7 100644
--- a/opcodes.h
+++ b/opcodes.h
@@ -26,161 +26,162 @@ struct opcode {
26 void (*instr)(uint16_t arg); 26 void (*instr)(uint16_t arg);
27 uint8_t bytes; 27 uint8_t bytes;
28 uint8_t cycles; 28 uint8_t cycles;
29 bool didmemory; 29 bool memread;
30 bool memwrite;
30 enum addressing_mode mode; 31 enum addressing_mode mode;
31}; 32};
32 33
33struct opcode opcodes[0x100] = { 34struct opcode opcodes[0x100] = {
34 /* official opcodes */ 35 /* official opcodes */
35 [0x69] = { "ADC", ADC, 2, 2, false, AM_IMM }, 36 [0x69] = { "ADC", ADC, 2, 2, false, false, AM_IMM },
36 [0x65] = { "ADC", ADC, 2, 3, false, AM_ZP }, 37 [0x65] = { "ADC", ADC, 2, 3, false, false, AM_ZP },
37 [0x75] = { "ADC", ADC, 2, 4, false, AM_ZP_X }, 38 [0x75] = { "ADC", ADC, 2, 4, false, false, AM_ZP_X },
38 [0x6D] = { "ADC", ADC, 3, 4, false, AM_ABS }, 39 [0x6D] = { "ADC", ADC, 3, 4, false, false, AM_ABS },
39 [0x7D] = { "ADC", ADC, 3, 4, false, AM_ABS_X }, 40 [0x7D] = { "ADC", ADC, 3, 4, false, false, AM_ABS_X },
40 [0x79] = { "ADC", ADC, 3, 4, false, AM_ABS_Y }, 41 [0x79] = { "ADC", ADC, 3, 4, false, false, AM_ABS_Y },
41 [0x61] = { "ADC", ADC, 2, 6, false, AM_IND_X }, 42 [0x61] = { "ADC", ADC, 2, 6, false, false, AM_IND_X },
42 [0x71] = { "ADC", ADC, 2, 5, false, AM_IND_Y }, 43 [0x71] = { "ADC", ADC, 2, 5, false, false, AM_IND_Y },
43 [0x29] = { "AND", AND, 2, 2, false, AM_IMM }, 44 [0x29] = { "AND", AND, 2, 2, false, false, AM_IMM },
44 [0x25] = { "AND", AND, 2, 3, false, AM_ZP }, 45 [0x25] = { "AND", AND, 2, 3, false, false, AM_ZP },
45 [0x35] = { "AND", AND, 2, 4, false, AM_ZP_X }, 46 [0x35] = { "AND", AND, 2, 4, false, false, AM_ZP_X },
46 [0x2D] = { "AND", AND, 3, 4, false, AM_ABS }, 47 [0x2D] = { "AND", AND, 3, 4, false, false, AM_ABS },
47 [0x3D] = { "AND", AND, 3, 4, false, AM_ABS_X }, 48 [0x3D] = { "AND", AND, 3, 4, false, false, AM_ABS_X },
48 [0x39] = { "AND", AND, 3, 4, false, AM_ABS_Y }, 49 [0x39] = { "AND", AND, 3, 4, false, false, AM_ABS_Y },
49 [0x21] = { "AND", AND, 2, 6, false, AM_IND_X }, 50 [0x21] = { "AND", AND, 2, 6, false, false, AM_IND_X },
50 [0x31] = { "AND", AND, 2, 5, false, AM_IND_Y }, 51 [0x31] = { "AND", AND, 2, 5, false, false, AM_IND_Y },
51 [0x0A] = { "ASL", ASL_acc, 1, 2, false, AM_ACC }, 52 [0x0A] = { "ASL", ASL_acc, 1, 2, false, false, AM_ACC },
52 [0x06] = { "ASL", ASL, 2, 5, true, AM_ZP }, 53 [0x06] = { "ASL", ASL, 2, 5, false, true, AM_ZP },
53 [0x16] = { "ASL", ASL, 2, 6, true, AM_ZP_X }, 54 [0x16] = { "ASL", ASL, 2, 6, false, true, AM_ZP_X },
54 [0x0E] = { "ASL", ASL, 3, 6, true, AM_ABS }, 55 [0x0E] = { "ASL", ASL, 3, 6, false, true, AM_ABS },
55 [0x1E] = { "ASL", ASL, 3, 7, true, AM_ABS_X }, 56 [0x1E] = { "ASL", ASL, 3, 7, false, true, AM_ABS_X },
56 [0x90] = { "BCC", BCC, 2, 2, false, AM_REL }, 57 [0x90] = { "BCC", BCC, 2, 2, false, false, AM_REL },
57 [0xB0] = { "BCS", BCS, 2, 2, false, AM_REL }, 58 [0xB0] = { "BCS", BCS, 2, 2, false, false, AM_REL },
58 [0xF0] = { "BEQ", BEQ, 2, 2, false, AM_REL }, 59 [0xF0] = { "BEQ", BEQ, 2, 2, false, false, AM_REL },
59 [0x24] = { "BIT", BIT, 2, 3, true, AM_ZP }, 60 [0x24] = { "BIT", BIT, 2, 3, true, false, AM_ZP },
60 [0x2C] = { "BIT", BIT, 3, 4, true, AM_ABS }, 61 [0x2C] = { "BIT", BIT, 3, 4, true, false, AM_ABS },
61 [0x30] = { "BMI", BMI, 2, 2, false, AM_REL }, 62 [0x30] = { "BMI", BMI, 2, 2, false, false, AM_REL },
62 [0xD0] = { "BNE", BNE, 2, 2, false, AM_REL }, 63 [0xD0] = { "BNE", BNE, 2, 2, false, false, AM_REL },
63 [0x10] = { "BPL", BPL, 2, 2, false, AM_REL }, 64 [0x10] = { "BPL", BPL, 2, 2, false, false, AM_REL },
64 [0x00] = { "BRK", BRK, 1, 7, false, AM_NONE }, 65 [0x00] = { "BRK", BRK, 1, 7, false, false, AM_NONE },
65 [0x50] = { "BVC", BVC, 2, 2, false, AM_REL }, 66 [0x50] = { "BVC", BVC, 2, 2, false, false, AM_REL },
66 [0x70] = { "BVS", BVS, 2, 2, false, AM_REL }, 67 [0x70] = { "BVS", BVS, 2, 2, false, false, AM_REL },
67 [0x18] = { "CLC", CLC, 1, 2, false, AM_NONE }, 68 [0x18] = { "CLC", CLC, 1, 2, false, false, AM_NONE },
68 [0xD8] = { "CLD", CLD, 1, 2, false, AM_NONE }, 69 [0xD8] = { "CLD", CLD, 1, 2, false, false, AM_NONE },
69 [0x58] = { "CLI", CLI, 1, 2, false, AM_NONE }, 70 [0x58] = { "CLI", CLI, 1, 2, false, false, AM_NONE },
70 [0xB8] = { "CLV", CLV, 1, 2, false, AM_NONE }, 71 [0xB8] = { "CLV", CLV, 1, 2, false, false, AM_NONE },
71 [0xC9] = { "CMP", CMP, 2, 2, false, AM_IMM }, 72 [0xC9] = { "CMP", CMP, 2, 2, false, false, AM_IMM },
72 [0xC5] = { "CMP", CMP, 2, 3, false, AM_ZP }, 73 [0xC5] = { "CMP", CMP, 2, 3, false, false, AM_ZP },
73 [0xD5] = { "CMP", CMP, 2, 4, false, AM_ZP_X }, 74 [0xD5] = { "CMP", CMP, 2, 4, false, false, AM_ZP_X },
74 [0xCD] = { "CMP", CMP, 3, 4, false, AM_ABS }, 75 [0xCD] = { "CMP", CMP, 3, 4, false, false, AM_ABS },
75 [0xDD] = { "CMP", CMP, 3, 4, false, AM_ABS_X }, 76 [0xDD] = { "CMP", CMP, 3, 4, false, false, AM_ABS_X },
76 [0xD9] = { "CMP", CMP, 3, 4, false, AM_ABS_Y }, 77 [0xD9] = { "CMP", CMP, 3, 4, false, false, AM_ABS_Y },
77 [0xC1] = { "CMP", CMP, 2, 6, false, AM_IND_X }, 78 [0xC1] = { "CMP", CMP, 2, 6, false, false, AM_IND_X },
78 [0xD1] = { "CMP", CMP, 2, 5, false, AM_IND_Y }, 79 [0xD1] = { "CMP", CMP, 2, 5, false, false, AM_IND_Y },
79 [0xE0] = { "CPX", CPX, 2, 2, false, AM_IMM }, 80 [0xE0] = { "CPX", CPX, 2, 2, false, false, AM_IMM },
80 [0xE4] = { "CPX", CPX, 2, 3, false, AM_ZP }, 81 [0xE4] = { "CPX", CPX, 2, 3, false, false, AM_ZP },
81 [0xEC] = { "CPX", CPX, 3, 4, false, AM_ABS }, 82 [0xEC] = { "CPX", CPX, 3, 4, false, false, AM_ABS },
82 [0xC0] = { "CPY", CPY, 2, 2, false, AM_IMM }, 83 [0xC0] = { "CPY", CPY, 2, 2, false, false, AM_IMM },
83 [0xC4] = { "CPY", CPY, 2, 3, false, AM_ZP }, 84 [0xC4] = { "CPY", CPY, 2, 3, false, false, AM_ZP },
84 [0xCC] = { "CPY", CPY, 3, 4, false, AM_ABS }, 85 [0xCC] = { "CPY", CPY, 3, 4, false, false, AM_ABS },
85 [0xC6] = { "DEC", DEC, 2, 5, true, AM_ZP }, 86 [0xC6] = { "DEC", DEC, 2, 5, false, true, AM_ZP },
86 [0xD6] = { "DEC", DEC, 2, 6, true, AM_ZP_X }, 87 [0xD6] = { "DEC", DEC, 2, 6, false, true, AM_ZP_X },
87 [0xCE] = { "DEC", DEC, 3, 6, true, AM_ABS }, 88 [0xCE] = { "DEC", DEC, 3, 6, false, true, AM_ABS },
88 [0xDE] = { "DEC", DEC, 3, 7, true, AM_ABS_X }, 89 [0xDE] = { "DEC", DEC, 3, 7, false, true, AM_ABS_X },
89 [0xCA] = { "DEX", DEX, 1, 2, false, AM_NONE }, 90 [0xCA] = { "DEX", DEX, 1, 2, false, false, AM_NONE },
90 [0x88] = { "DEY", DEY, 1, 2, false, AM_NONE }, 91 [0x88] = { "DEY", DEY, 1, 2, false, false, AM_NONE },
91 [0x49] = { "EOR", EOR, 2, 2, false, AM_IMM }, 92 [0x49] = { "EOR", EOR, 2, 2, false, false, AM_IMM },
92 [0x45] = { "EOR", EOR, 2, 3, false, AM_ZP }, 93 [0x45] = { "EOR", EOR, 2, 3, false, false, AM_ZP },
93 [0x55] = { "EOR", EOR, 2, 4, false, AM_ZP_X }, 94 [0x55] = { "EOR", EOR, 2, 4, false, false, AM_ZP_X },
94 [0x4D] = { "EOR", EOR, 3, 4, false, AM_ABS }, 95 [0x4D] = { "EOR", EOR, 3, 4, false, false, AM_ABS },
95 [0x5D] = { "EOR", EOR, 3, 4, false, AM_ABS_X }, 96 [0x5D] = { "EOR", EOR, 3, 4, false, false, AM_ABS_X },
96 [0x59] = { "EOR", EOR, 3, 4, false, AM_ABS_Y }, 97 [0x59] = { "EOR", EOR, 3, 4, false, false, AM_ABS_Y },
97 [0x41] = { "EOR", EOR, 2, 6, false, AM_IND_X }, 98 [0x41] = { "EOR", EOR, 2, 6, false, false, AM_IND_X },
98 [0x51] = { "EOR", EOR, 2, 5, false, AM_IND_Y }, 99 [0x51] = { "EOR", EOR, 2, 5, false, false, AM_IND_Y },
99 [0xE6] = { "INC", INC, 2, 5, true, AM_ZP }, 100 [0xE6] = { "INC", INC, 2, 5, false, true, AM_ZP },
100 [0xF6] = { "INC", INC, 2, 6, true, AM_ZP_X }, 101 [0xF6] = { "INC", INC, 2, 6, false, true, AM_ZP_X },
101 [0xEE] = { "INC", INC, 3, 6, true, AM_ABS }, 102 [0xEE] = { "INC", INC, 3, 6, false, true, AM_ABS },
102 [0xFE] = { "INC", INC, 3, 7, true, AM_ABS_X }, 103 [0xFE] = { "INC", INC, 3, 7, false, true, AM_ABS_X },
103 [0xE8] = { "INX", INX, 1, 2, false, AM_NONE }, 104 [0xE8] = { "INX", INX, 1, 2, false, false, AM_NONE },
104 [0xC8] = { "INY", INY, 1, 2, false, AM_NONE }, 105 [0xC8] = { "INY", INY, 1, 2, false, false, AM_NONE },
105 [0x4C] = { "JMP", JMP, 3, 3, false, AM_ABS }, 106 [0x4C] = { "JMP", JMP, 3, 3, false, false, AM_ABS },
106 [0x6C] = { "JMP", JMP, 3, 5, false, AM_IND }, 107 [0x6C] = { "JMP", JMP, 3, 5, false, false, AM_IND },
107 [0x20] = { "JSR", JSR, 3, 6, false, AM_ABS }, 108 [0x20] = { "JSR", JSR, 3, 6, false, false, AM_ABS },
108 [0xA9] = { "LDA", LDA, 2, 2, false, AM_IMM }, 109 [0xA9] = { "LDA", LDA, 2, 2, false, false, AM_IMM },
109 [0xA5] = { "LDA", LDA, 2, 3, false, AM_ZP }, 110 [0xA5] = { "LDA", LDA, 2, 3, true, false, AM_ZP },
110 [0xB5] = { "LDA", LDA, 2, 4, false, AM_ZP_X }, 111 [0xB5] = { "LDA", LDA, 2, 4, true, false, AM_ZP_X },
111 [0xAD] = { "LDA", LDA, 3, 4, false, AM_ABS }, 112 [0xAD] = { "LDA", LDA, 3, 4, true, false, AM_ABS },
112 [0xBD] = { "LDA", LDA, 3, 4, false, AM_ABS_X }, 113 [0xBD] = { "LDA", LDA, 3, 4, true, false, AM_ABS_X },
113 [0xB9] = { "LDA", LDA, 3, 4, false, AM_ABS_Y }, 114 [0xB9] = { "LDA", LDA, 3, 4, true, false, AM_ABS_Y },
114 [0xA1] = { "LDA", LDA, 2, 6, false, AM_IND_X }, 115 [0xA1] = { "LDA", LDA, 2, 6, true, false, AM_IND_X },
115 [0xB1] = { "LDA", LDA, 2, 5, false, AM_IND_Y }, 116 [0xB1] = { "LDA", LDA, 2, 5, true, false, AM_IND_Y },
116 [0xA2] = { "LDX", LDX, 2, 2, false, AM_IMM }, 117 [0xA2] = { "LDX", LDX, 2, 2, false, false, AM_IMM },
117 [0xA6] = { "LDX", LDX, 2, 3, true, AM_ZP }, 118 [0xA6] = { "LDX", LDX, 2, 3, true, false, AM_ZP },
118 [0xB6] = { "LDX", LDX, 2, 4, false, AM_ZP_Y }, 119 [0xB6] = { "LDX", LDX, 2, 4, true, false, AM_ZP_Y },
119 [0xAE] = { "LDX", LDX, 3, 4, true, AM_ABS }, 120 [0xAE] = { "LDX", LDX, 3, 4, true, false, AM_ABS },
120 [0xBE] = { "LDX", LDX, 3, 4, false, AM_ABS_Y }, 121 [0xBE] = { "LDX", LDX, 3, 4, true, false, AM_ABS_Y },
121 [0xA0] = { "LDY", LDY, 2, 2, false, AM_IMM }, 122 [0xA0] = { "LDY", LDY, 2, 2, false, false, AM_IMM },
122 [0xA4] = { "LDY", LDY, 2, 3, false, AM_ZP }, 123 [0xA4] = { "LDY", LDY, 2, 3, true, false, AM_ZP },
123 [0xB4] = { "LDY", LDY, 2, 4, false, AM_ZP_X }, 124 [0xB4] = { "LDY", LDY, 2, 4, true, false, AM_ZP_X },
124 [0xAC] = { "LDY", LDY, 3, 4, false, AM_ABS }, 125 [0xAC] = { "LDY", LDY, 3, 4, true, false, AM_ABS },
125 [0xBC] = { "LDY", LDY, 3, 4, false, AM_ABS_X }, 126 [0xBC] = { "LDY", LDY, 3, 4, true, false, AM_ABS_X },
126 [0x4A] = { "LSR", LSR_acc, 1, 2, false, AM_ACC }, 127 [0x4A] = { "LSR", LSR_acc, 1, 2, false, false, AM_ACC },
127 [0x46] = { "LSR", LSR, 2, 5, true, AM_ZP }, 128 [0x46] = { "LSR", LSR, 2, 5, false, true, AM_ZP },
128 [0x56] = { "LSR", LSR, 2, 6, true, AM_ZP_X }, 129 [0x56] = { "LSR", LSR, 2, 6, false, true, AM_ZP_X },
129 [0x4E] = { "LSR", LSR, 3, 6, true, AM_ABS }, 130 [0x4E] = { "LSR", LSR, 3, 6, false, true, AM_ABS },
130 [0x5E] = { "LSR", LSR, 3, 7, true, AM_ABS_X }, 131 [0x5E] = { "LSR", LSR, 3, 7, false, true, AM_ABS_X },
131 [0xEA] = { "NOP", NOP, 1, 2, false, AM_NONE }, 132 [0xEA] = { "NOP", NOP, 1, 2, false, false, AM_NONE },
132 [0x09] = { "ORA", ORA, 2, 2, false, AM_IMM }, 133 [0x09] = { "ORA", ORA, 2, 2, false, false, AM_IMM },
133 [0x05] = { "ORA", ORA, 2, 3, false, AM_ZP }, 134 [0x05] = { "ORA", ORA, 2, 3, false, false, AM_ZP },
134 [0x15] = { "ORA", ORA, 2, 4, false, AM_ZP_X }, 135 [0x15] = { "ORA", ORA, 2, 4, false, false, AM_ZP_X },
135 [0x0D] = { "ORA", ORA, 3, 4, false, AM_ABS }, 136 [0x0D] = { "ORA", ORA, 3, 4, false, false, AM_ABS },
136 [0x1D] = { "ORA", ORA, 3, 4, false, AM_ABS_X }, 137 [0x1D] = { "ORA", ORA, 3, 4, false, false, AM_ABS_X },
137 [0x19] = { "ORA", ORA, 3, 4, false, AM_ABS_Y }, 138 [0x19] = { "ORA", ORA, 3, 4, false, false, AM_ABS_Y },
138 [0x01] = { "ORA", ORA, 2, 6, false, AM_IND_X }, 139 [0x01] = { "ORA", ORA, 2, 6, false, false, AM_IND_X },
139 [0x11] = { "ORA", ORA, 2, 5, false, AM_IND_Y }, 140 [0x11] = { "ORA", ORA, 2, 5, false, false, AM_IND_Y },
140 [0x48] = { "PHA", PHA, 1, 3, false, AM_NONE }, 141 [0x48] = { "PHA", PHA, 1, 3, false, false, AM_NONE },
141 [0x08] = { "PHP", PHP, 1, 3, false, AM_NONE }, 142 [0x08] = { "PHP", PHP, 1, 3, false, false, AM_NONE },
142 [0x68] = { "PLA", PLA, 1, 4, false, AM_NONE }, 143 [0x68] = { "PLA", PLA, 1, 4, false, false, AM_NONE },
143 [0x28] = { "PLP", PLP, 1, 4, false, AM_NONE }, 144 [0x28] = { "PLP", PLP, 1, 4, false, false, AM_NONE },
144 [0x2A] = { "ROL", ROL_acc, 1, 2, false, AM_ACC }, 145 [0x2A] = { "ROL", ROL_acc, 1, 2, false, false, AM_ACC },
145 [0x26] = { "ROL", ROL, 2, 5, true, AM_ZP }, 146 [0x26] = { "ROL", ROL, 2, 5, false, true, AM_ZP },
146 [0x36] = { "ROL", ROL, 2, 6, true, AM_ZP_X }, 147 [0x36] = { "ROL", ROL, 2, 6, false, true, AM_ZP_X },
147 [0x2E] = { "ROL", ROL, 3, 6, true, AM_ABS }, 148 [0x2E] = { "ROL", ROL, 3, 6, false, true, AM_ABS },
148 [0x3E] = { "ROL", ROL, 3, 7, true, AM_ABS_X }, 149 [0x3E] = { "ROL", ROL, 3, 7, false, true, AM_ABS_X },
149 [0x6A] = { "ROR", ROR_acc, 1, 2, false, AM_ACC }, 150 [0x6A] = { "ROR", ROR_acc, 1, 2, false, false, AM_ACC },
150 [0x66] = { "ROR", ROR, 2, 5, true, AM_ZP }, 151 [0x66] = { "ROR", ROR, 2, 5, false, true, AM_ZP },
151 [0x76] = { "ROR", ROR, 2, 6, true, AM_ZP_X }, 152 [0x76] = { "ROR", ROR, 2, 6, false, true, AM_ZP_X },
152 [0x6E] = { "ROR", ROR, 3, 6, true, AM_ABS }, 153 [0x6E] = { "ROR", ROR, 3, 6, false, true, AM_ABS },
153 [0x7E] = { "ROR", ROR, 3, 7, true, AM_ABS_X }, 154 [0x7E] = { "ROR", ROR, 3, 7, false, true, AM_ABS_X },
154 [0x40] = { "RTI", RTI, 1, 6, false, AM_NONE }, 155 [0x40] = { "RTI", RTI, 1, 6, false, false, AM_NONE },
155 [0x60] = { "RTS", RTS, 1, 6, false, AM_NONE }, 156 [0x60] = { "RTS", RTS, 1, 6, false, false, AM_NONE },
156 [0xE9] = { "SBC", SBC, 2, 2, false, AM_IMM }, 157 [0xE9] = { "SBC", SBC, 2, 2, false, false, AM_IMM },
157 [0xE5] = { "SBC", SBC, 2, 3, false, AM_ZP }, 158 [0xE5] = { "SBC", SBC, 2, 3, false, false, AM_ZP },
158 [0xF5] = { "SBC", SBC, 2, 4, false, AM_ZP_X }, 159 [0xF5] = { "SBC", SBC, 2, 4, false, false, AM_ZP_X },
159 [0xED] = { "SBC", SBC, 3, 4, false, AM_ABS }, 160 [0xED] = { "SBC", SBC, 3, 4, false, false, AM_ABS },
160 [0xFD] = { "SBC", SBC, 3, 4, false, AM_ABS_X }, 161 [0xFD] = { "SBC", SBC, 3, 4, false, false, AM_ABS_X },
161 [0xF9] = { "SBC", SBC, 3, 4, false, AM_ABS_Y }, 162 [0xF9] = { "SBC", SBC, 3, 4, false, false, AM_ABS_Y },
162 [0xE1] = { "SBC", SBC, 2, 6, false, AM_IND_X }, 163 [0xE1] = { "SBC", SBC, 2, 6, false, false, AM_IND_X },
163 [0xF1] = { "SBC", SBC, 2, 5, false, AM_IND_Y }, 164 [0xF1] = { "SBC", SBC, 2, 5, false, false, AM_IND_Y },
164 [0x38] = { "SEC", SEC, 1, 2, false, AM_NONE }, 165 [0x38] = { "SEC", SEC, 1, 2, false, false, AM_NONE },
165 [0xF8] = { "SED", SED, 1, 2, false, AM_NONE }, 166 [0xF8] = { "SED", SED, 1, 2, false, false, AM_NONE },
166 [0x78] = { "SEI", SEI, 1, 2, false, AM_NONE }, 167 [0x78] = { "SEI", SEI, 1, 2, false, false, AM_NONE },
167 [0x85] = { "STA", STA, 2, 3, true, AM_ZP }, 168 [0x85] = { "STA", STA, 2, 3, false, true, AM_ZP },
168 [0x95] = { "STA", STA, 2, 4, true, AM_ZP_X }, 169 [0x95] = { "STA", STA, 2, 4, false, true, AM_ZP_X },
169 [0x8D] = { "STA", STA, 3, 4, true, AM_ABS }, 170 [0x8D] = { "STA", STA, 3, 4, false, true, AM_ABS },
170 [0x9D] = { "STA", STA, 3, 5, true, AM_ABS_X }, 171 [0x9D] = { "STA", STA, 3, 5, false, true, AM_ABS_X },
171 [0x99] = { "STA", STA, 3, 5, true, AM_ABS_Y }, 172 [0x99] = { "STA", STA, 3, 5, false, true, AM_ABS_Y },
172 [0x81] = { "STA", STA, 2, 6, true, AM_IND_X }, 173 [0x81] = { "STA", STA, 2, 6, false, true, AM_IND_X },
173 [0x91] = { "STA", STA, 2, 6, true, AM_IND_Y }, 174 [0x91] = { "STA", STA, 2, 6, false, true, AM_IND_Y },
174 [0x86] = { "STX", STX, 2, 3, true, AM_ZP }, 175 [0x86] = { "STX", STX, 2, 3, false, true, AM_ZP },
175 [0x96] = { "STX", STX, 2, 4, true, AM_ZP_Y }, 176 [0x96] = { "STX", STX, 2, 4, false, true, AM_ZP_Y },
176 [0x8E] = { "STX", STX, 3, 4, true, AM_ABS }, 177 [0x8E] = { "STX", STX, 3, 4, false, true, AM_ABS },
177 [0x84] = { "STY", STY, 2, 3, true, AM_ZP }, 178 [0x84] = { "STY", STY, 2, 3, false, true, AM_ZP },
178 [0x94] = { "STY", STY, 2, 4, true, AM_ZP_X }, 179 [0x94] = { "STY", STY, 2, 4, false, true, AM_ZP_X },
179 [0x8C] = { "STY", STY, 3, 4, true, AM_ABS }, 180 [0x8C] = { "STY", STY, 3, 4, false, true, AM_ABS },
180 [0xAA] = { "TAX", TAX, 1, 2, false, AM_NONE }, 181 [0xAA] = { "TAX", TAX, 1, 2, false, false, AM_NONE },
181 [0xA8] = { "TAY", TAY, 1, 2, false, AM_NONE }, 182 [0xA8] = { "TAY", TAY, 1, 2, false, false, AM_NONE },
182 [0xBA] = { "TSX", TSX, 1, 2, false, AM_NONE }, 183 [0xBA] = { "TSX", TSX, 1, 2, false, false, AM_NONE },
183 [0x8A] = { "TXA", TXA, 1, 2, false, AM_NONE }, 184 [0x8A] = { "TXA", TXA, 1, 2, false, false, AM_NONE },
184 [0x9A] = { "TXS", TXS, 1, 2, false, AM_NONE }, 185 [0x9A] = { "TXS", TXS, 1, 2, false, false, AM_NONE },
185 [0x98] = { "TYA", TYA, 1, 2, false, AM_NONE }, 186 [0x98] = { "TYA", TYA, 1, 2, false, false, AM_NONE },
186}; 187};
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-03 05:14:18 +0000