1 files changed, 6 insertions, 0 deletions
diff --git a/lang/verilator/pkg/DESCR b/lang/verilator/pkg/DESCR
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+Verilator is the fastest free Verilog HDL simulator, and beats most
+commercial simulators. It compiles synthesizable Verilog (not test-bench
+code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
+or SystemC code. It is designed for large projects where fast simulation
+performance is of primary concern, and is especially well suited to
+generate executable models of CPUs for embedded software design teams.

diff --git a/lang/verilator/pkg/DESCR b/lang/verilator/pkg/DESCR new file mode 100644 index 0000000..24bde1a --- /dev/null +++ b/lang/verilator/pkg/DESCR
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	1	Verilator is the fastest free Verilog HDL simulator, and beats most
	2	commercial simulators. It compiles synthesizable Verilog (not test-bench
	3	code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
	4	or SystemC code. It is designed for large projects where fast simulation
	5	performance is of primary concern, and is especially well suited to
	6	generate executable models of CPUs for embedded software design teams.