[Core] STM32G0x1 support (#24301)

7 files changed, 538 insertions, 2 deletions

diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk
new file mode 100644
index 0000000000..7e551e4dc7
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk
@@ -0,0 +1,12 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G0B1RE/board.c
+
+# Extra files
+BOARDSRC += $(BOARD_PATH)/board/extra.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G0B1RE
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c
new file mode 100644
index 0000000000..4dbc5dd8b4
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c
@@ -0,0 +1,68 @@
+// Copyright 2025 Stefan Kerkmann (@karlk90)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <hal.h>
+
+#define FLASH_KEY1 0x45670123U
+#define FLASH_KEY2 0xCDEF89ABU
+#define FLASH_OPTKEY1 0x08192A3BU
+#define FLASH_OPTKEY2 0x4C5D6E7FU
+#define FLASH_OPTR_CLR_MASK (FLASH_OPTR_nBOOT_SEL)
+#define FLASH_OPTR_SET_MASK (FLASH_OPTR_NRST_MODE_Msk)
+
+static void wait_for_flash(void) {
+    while (READ_BIT(FLASH->SR, FLASH_SR_BSY1)) {
+    }
+}
+
+void __attribute__((constructor)) enable_boot0_and_nrst_pin(void) {
+    // Only apply on STM32G0x1 devices, see RM0444 Rev 6, Table 265: "DEV_ID
+    // and REV_ID field values."
+    switch (READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID)) {
+        case 0x467: // STM32G0B1xx and STM32G0C1xx
+        case 0x460: // STM32G071xx and STM32G081xx
+        case 0x456: // STM32G051xx and STM32G061xx
+        case 0x466: // STM32G041xx and STM32G031xx
+            break;
+        default:
+            return;
+    }
+
+    uint32_t optr = FLASH->OPTR;
+
+    // Make sure that:
+    // 1. legacy boot0 pin handling is enabled.
+    //   OPTR[24] = 0
+    // 2. legacy nRST pin handling is enabled.
+    //   OPTR[28:27] = 0b11
+    // To match the default behavior found in older (F0/F1/F3/F4) STM32 devices.
+    if (READ_BIT(optr, FLASH_OPTR_CLR_MASK) || (READ_BIT(optr, FLASH_OPTR_SET_MASK) != FLASH_OPTR_SET_MASK)) {
+        if (READ_BIT(FLASH->CR, FLASH_CR_LOCK)) {
+            WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+            WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+            while (READ_BIT(FLASH->CR, FLASH_CR_LOCK)) {
+            }
+            wait_for_flash();
+        }
+        if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK)) {
+            WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+            WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+            while (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK)) {
+            }
+            wait_for_flash();
+        }
+
+        MODIFY_REG(FLASH->OPTR, FLASH_OPTR_CLR_MASK, FLASH_OPTR_SET_MASK);
+        wait_for_flash();
+
+        SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+        wait_for_flash();
+
+        CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+        wait_for_flash();
+
+        // Launch the option byte (re)loading, which resets the device. This
+        // should not return.
+        SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+    }
+}
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h
new file mode 100644
index 0000000000..bb2d1b5816
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h
@@ -0,0 +1,7 @@
+// Copyright 2024 Stefan Kerkmann (@karlk90)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
new file mode 100644
index 0000000000..80726e0308
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
@@ -0,0 +1,310 @@
+/*
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32G0xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 3...0        Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+#define STM32G0xx_MCUCONF
+#define STM32G0B1_MCUCONF
+#define STM32G0C1_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_CLOCK_DYNAMIC                 TRUE
+#define STM32_VOS                           STM32_VOS_RANGE1
+#define STM32_PWR_CR2                       (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
+#define STM32_PWR_CR3                       (PWR_CR3_EIWUL)
+#define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_HSIDIV_VALUE                  1
+#define STM32_HSI16_ENABLED                 TRUE
+#define STM32_HSI48_ENABLED                 TRUE
+#define STM32_HSE_ENABLED                   FALSE
+#define STM32_LSI_ENABLED                   FALSE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_SW                            STM32_SW_PLLRCLK
+#define STM32_PLLSRC                        STM32_PLLSRC_HSI16
+#define STM32_PLLM_VALUE                    2
+#define STM32_PLLN_VALUE                    16
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    4
+#define STM32_PLLR_VALUE                    2
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE                          STM32_PPRE_DIV1
+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
+#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
+#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+
+/*
+ * Peripherals clocks and sources.
+ */
+#define STM32_FDCANSEL                      STM32_USBSEL_HSI48
+#define STM32_USBSEL                        STM32_USBSEL_HSI48
+#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
+#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
+#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART2SEL                    STM32_LPUART2SEL_SYSCLK
+#define STM32_CECSEL                        STM32_CECSEL_HSI16DIV
+#define STM32_I2C1SEL                       STM32_I2C1SEL_PCLK
+#define STM32_I2C2SEL                       STM32_I2C1SEL_PCLK
+#define STM32_I2S1SEL                       STM32_I2S1SEL_SYSCLK
+#define STM32_I2S2SEL                       STM32_I2S2SEL_SYSCLK
+#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK
+#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK
+#define STM32_TIM1SEL                       STM32_TIM1SEL_TIMPCLK
+#define STM32_TIM15SEL                      STM32_TIM15SEL_TIMPCLK
+#define STM32_RNGSEL                        STM32_RNGSEL_HSI16
+#define STM32_RNGDIV_VALUE                  1
+#define STM32_ADCSEL                        STM32_ADCSEL_PLLPCLK
+#define STM32_RTCSEL                        STM32_RTCSEL_NOCLOCK
+
+/*
+ * Shared IRQ settings.
+ */
+#define STM32_IRQ_EXTI0_1_PRIORITY          3
+#define STM32_IRQ_EXTI2_3_PRIORITY          3
+#define STM32_IRQ_EXTI4_15_PRIORITY         3
+#define STM32_IRQ_EXTI1921_PRIORITY         3
+
+#define STM32_IRQ_USART1_PRIORITY           2
+#define STM32_IRQ_USART2_LP2_PRIORITY       2
+#define STM32_IRQ_USART3_4_5_6_LP1_PRIORITY 2
+
+#define STM32_IRQ_TIM1_UP_PRIORITY          1
+#define STM32_IRQ_TIM1_CC_PRIORITY          1
+#define STM32_IRQ_TIM2_PRIORITY             1
+#define STM32_IRQ_TIM3_4_PRIORITY           1
+#define STM32_IRQ_TIM6_PRIORITY             1
+#define STM32_IRQ_TIM7_PRIORITY             1
+#define STM32_IRQ_TIM14_PRIORITY            1
+#define STM32_IRQ_TIM15_PRIORITY            1
+#define STM32_IRQ_TIM16_PRIORITY            1
+#define STM32_IRQ_TIM17_PRIORITY            1
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_ADC1_CFGR2                ADC_CFGR2_CKMODE_ADCCLK
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_PRESCALER_VALUE           2
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE                 FALSE
+#define STM32_DAC_USE_DAC1_CH1              FALSE
+#define STM32_DAC_USE_DAC1_CH2              FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     3
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     3
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM6                  FALSE
+#define STM32_GPT_USE_TIM7                  FALSE
+#define STM32_GPT_USE_TIM14                 FALSE
+#define STM32_GPT_USE_TIM15                 FALSE
+#define STM32_GPT_USE_TIM16                 FALSE
+#define STM32_GPT_USE_TIM17                 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_BUSY_TIMEOUT              50
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_IRQ_PRIORITY         3
+#define STM32_I2C_I2C2_IRQ_PRIORITY         3
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM15                 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  FALSE
+#define STM32_PWM_USE_TIM14                 FALSE
+#define STM32_PWM_USE_TIM15                 FALSE
+#define STM32_PWM_USE_TIM16                 FALSE
+#define STM32_PWM_USE_TIM17                 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE               32
+#define STM32_RTC_PRESS_VALUE               1024
+#define STM32_RTC_CR_INIT                   0
+#define STM32_RTC_TAMPCR_INIT               0
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             FALSE
+#define STM32_SERIAL_USE_USART3             FALSE
+#define STM32_SERIAL_USE_UART4              FALSE
+#define STM32_SERIAL_USE_UART5              FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+#define STM32_SERIAL_USE_LPUART1            FALSE
+#define STM32_SERIAL_USE_LPUART2            FALSE
+
+/*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1                FALSE
+#define STM32_SIO_USE_USART2                FALSE
+#define STM32_SIO_USE_USART3                FALSE
+#define STM32_SIO_USE_UART4                 FALSE
+#define STM32_SIO_USE_UART5                 FALSE
+#define STM32_SIO_USE_USART6                FALSE
+#define STM32_SIO_USE_LPUART1               FALSE
+#define STM32_SIO_USE_LPUART2               FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  FALSE
+#define STM32_SPI_USE_SPI3                  FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         2
+#define STM32_SPI_SPI2_IRQ_PRIORITY         2
+#define STM32_SPI_SPI3_IRQ_PRIORITY         2
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               2
+#define STM32_ST_USE_TIMER                  2
+
+/*
+ * TRNG driver system settings.
+ * NOTE: STM32G0C1 only.
+ */
+#define STM32_TRNG_USE_RNG1                 FALSE
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART3               FALSE
+#define STM32_UART_USE_UART4                FALSE
+#define STM32_UART_USE_UART5                FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#define STM32_UART_UART4_DMA_PRIORITY       0
+#define STM32_UART_UART5_DMA_PRIORITY       0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_USB1                  TRUE
+#define STM32_USB_USB1_LP_IRQ_PRIORITY      3
+#define STM32_USB_USE_ISOCHRONOUS           FALSE
+#define STM32_USB_USE_FAST_COPY             TRUE
+#define STM32_USB_HOST_WAKEUP_DURATION      2
+#define STM32_USB_48MHZ_DELTA               0
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG                  FALSE
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/common/ld/STM32G0B1xB.ld b/platforms/chibios/boards/common/ld/STM32G0B1xB.ld
new file mode 100644
index 0000000000..0109504992
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32G0B1xB.ld
@@ -0,0 +1,85 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32G0B1xB memory setup.
+ */
+MEMORY
+{
+    flash0 (rx) : org = 0x08000000, len = 128k
+    flash1 (rx) : org = 0x00000000, len = 0
+    flash2 (rx) : org = 0x00000000, len = 0
+    flash3 (rx) : org = 0x00000000, len = 0
+    flash4 (rx) : org = 0x00000000, len = 0
+    flash5 (rx) : org = 0x00000000, len = 0
+    flash6 (rx) : org = 0x00000000, len = 0
+    flash7 (rx) : org = 0x00000000, len = 0
+    ram0   (wx) : org = 0x20000000, len = 144k
+    ram1   (wx) : org = 0x00000000, len = 0
+    ram2   (wx) : org = 0x00000000, len = 0
+    ram3   (wx) : org = 0x00000000, len = 0
+    ram4   (wx) : org = 0x00000000, len = 0
+    ram5   (wx) : org = 0x00000000, len = 0
+    ram6   (wx) : org = 0x00000000, len = 0
+    ram7   (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
index 7e1f87e6c9..a916cc9a1d 100644
--- a/platforms/chibios/drivers/analog.c
+++ b/platforms/chibios/drivers/analog.c
@@ -43,7 +43,7 @@
 #endif
 
 // Otherwise assume V3
-#if defined(STM32F0XX) || defined(STM32L0XX)
+#if defined(STM32F0XX) || defined(STM32L0XX) || defined(STM32G0XX)
 #    define USE_ADCV1
 #elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
 #    define USE_ADCV2
@@ -82,7 +82,7 @@
 
 /* User configurable ADC options */
 #ifndef ADC_COUNT
-#    if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
+#    if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
 #        define ADC_COUNT 1
 #    elif defined(STM32F3XX) || defined(STM32G4XX)
 #        define ADC_COUNT 4
@@ -114,6 +114,8 @@
 #        define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5
 #    elif defined(ADC_SMPR_SMP_2P5) // STM32L4XX, STM32L4XXP, STM32G4XX, STM32WBXX
 #        define ADC_SAMPLING_RATE ADC_SMPR_SMP_2P5
+#    elif defined(ADC_SMPR_SMP1_1P5) // STM32G0XX
+#        define ADC_SAMPLING_RATE ADC_SMPR_SMP1_1P5
 #    else
 #        error "Cannot determine the default ADC_SAMPLING_RATE for this MCU."
 #    endif
@@ -293,6 +295,23 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
         case F9:  return TO_MUX( ADC_CHANNEL_IN12, 2 );
         case F10: return TO_MUX( ADC_CHANNEL_IN13, 2 );
 #    endif
+#elif defined(STM32G0XX)
+        case A0:  return TO_MUX( 0,  0 );
+        case A1:  return TO_MUX( 1,  0 );
+        case A2:  return TO_MUX( 2,  0 );
+        case A3:  return TO_MUX( 3,  0 );
+        case A4:  return TO_MUX( 4,  0 );
+        case A5:  return TO_MUX( 5,  0 );
+        case A6:  return TO_MUX( 6,  0 );
+        case A7:  return TO_MUX( 7,  0 );
+        case B0:  return TO_MUX( 8,  0 );
+        case B1:  return TO_MUX( 9,  0 );
+        case B2:  return TO_MUX( 10, 0 );
+        case B10: return TO_MUX( 11, 0 );
+        case B11: return TO_MUX( 15, 0 );
+        case B12: return TO_MUX( 16, 0 );
+        case C4:  return TO_MUX( 17, 0 );
+        case C5:  return TO_MUX( 18, 0 );
 #elif defined(STM32G4XX)
         case A0:  return TO_MUX( ADC_CHANNEL_IN1,  0 ); // Can also be ADC2
         case A1:  return TO_MUX( ADC_CHANNEL_IN2,  0 ); // Can also be ADC2
diff --git a/platforms/chibios/mcu_selection.mk b/platforms/chibios/mcu_selection.mk
index 086a2b31c6..199bdb2321 100644
--- a/platforms/chibios/mcu_selection.mk
+++ b/platforms/chibios/mcu_selection.mk
@@ -511,6 +511,41 @@ ifneq ($(findstring STM32F446, $(MCU)),)
   EEPROM_DRIVER ?= transient
 endif
 
+ifneq ($(findstring STM32G0B1, $(MCU)),)
+  # Cortex version
+  MCU = cortex-m0plus
+
+  # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
+  ARMV = 6
+
+  ## chip/board settings
+  # - the next two should match the directories in
+  #   <chibios[-contrib]>/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)
+  #   OR
+  #   <chibios[-contrib]>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
+  MCU_FAMILY = STM32
+  MCU_SERIES = STM32G0xx
+
+  # Linker script to use
+  # - it should exist either in <chibios>/os/common/startup/ARMCMx/compilers/GCC/ld/
+  #   or <keyboard_dir>/ld/
+  MCU_LDSCRIPT ?= STM32G0B1xB
+
+  # Startup code to use
+  #  - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
+  MCU_STARTUP ?= stm32g0xx
+
+  # Board: it should exist either in <chibios>/os/hal/boards/,
+  # <keyboard_dir>/boards/, or drivers/boards/
+  BOARD ?= GENERIC_STM32_G0B1XB
+
+  # UF2 settings
+  UF2_FAMILY ?= STM32G0
+
+  # Bootloader address for STM32 DFU
+  STM32_BOOTLOADER_ADDRESS ?= 0x1FFF0000
+endif
+
 ifneq ($(findstring STM32G431, $(MCU)),)
   # Cortex version
   MCU = cortex-m4