summaryrefslogtreecommitdiff
path: root/tmk_core/protocol/arm_atsam/clks.h
diff options
context:
space:
mode:
Diffstat (limited to 'tmk_core/protocol/arm_atsam/clks.h')
-rw-r--r--tmk_core/protocol/arm_atsam/clks.h89
1 files changed, 0 insertions, 89 deletions
diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h
deleted file mode 100644
index 6ee71aff8f..0000000000
--- a/tmk_core/protocol/arm_atsam/clks.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2Copyright 2018 Massdrop Inc.
3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17
18#ifndef _CLKS_H_
19#define _CLKS_H_
20
21#ifndef MD_BOOTLOADER
22
23// From keyboard
24# include "config_led.h"
25# include "config.h"
26
27#endif // MD_BOOTLOADER
28
29#define PLL_RATIO 47 // mcu frequency ((X+1)MHz)
30#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock
31#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs
32#define FREQ_I2C0_DEFAULT 100000 // i2c to hub
33#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers
34#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution
35
36// I2C1 Set ~Result PWM Time (2x Drivers)
37// 1000000 1090000
38// 900000 1000000 3.82ms
39// 800000 860000
40// 700000 750000
41// 600000 630000
42// 580000 615000 6.08ms
43// 500000 522000
44
45#define FREQ_XOSC0 16000000
46
47#define CHAN_SERCOM_SPI 2 // shift regs
48#define CHAN_SERCOM_I2C0 0 // hub
49#define CHAN_SERCOM_I2C1 1 // led drivers
50#define CHAN_SERCOM_UART 3 // debug util
51
52// Generator clock channels
53#define GEN_DPLL0 0
54#define GEN_OSC0 1
55#define GEN_TC45 2
56
57#define SERCOM_COUNT 5
58#define GCLK_COUNT 12
59
60typedef struct clk_s {
61 uint32_t freq_dfll;
62 uint32_t freq_dpll[2];
63 uint32_t freq_sercom[SERCOM_COUNT];
64 uint32_t freq_gclk[GCLK_COUNT];
65 uint32_t freq_xosc0;
66 uint32_t freq_spi;
67 uint32_t freq_i2c0;
68 uint32_t freq_i2c1;
69 uint32_t freq_uart;
70 uint32_t freq_adc0;
71} clk_t;
72
73extern volatile clk_t system_clks;
74extern volatile uint64_t ms_clk;
75
76void CLK_oscctrl_init(void);
77void CLK_reset_time(void);
78uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq);
79uint32_t CLK_enable_timebase(void);
80uint64_t timer_read64(void);
81void CLK_delay_us(uint32_t usec);
82void CLK_delay_ms(uint64_t msec);
83
84uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq);
85uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq);
86uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq);
87void CLK_init(void);
88
89#endif // _CLKS_H_