rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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.gitignore (95B)

      1 #*
      2 obj_dir
      3 tests/.test_list
      4 design.json
      5 design_pnr.json
      6 *.rpt
      7 *.hex
      8 *.log
      9 *.dump
     10 runs/
     11 rom.txt