| 2026-08-21 23:46 | update README with current milestone | Vineet Kumar | 1 | +8 | -1 |
| 2026-08-21 23:31 | remove addi to nop decoding because of comparison | Vineet Kumar | 1 | +1 | -8 |
| 2026-08-21 22:55 | remove expensive redundant name-based opcode decoding | Vineet Kumar | 3 | +48 | -184 |
| 2026-08-11 11:40 | split memop into loadop and storeop | Vineet Kumar | 5 | +65 | -55 |
| 2026-08-09 11:24 | import riscv-tests' license and readme file | Vineet Kumar | 2 | +208 | -0 |
| 2026-08-07 09:10 | fold i-cache tag+valid into BSRAM to cut critical path | Vineet Kumar | 1 | +34 | -27 |
| 2026-08-07 07:01 | increase cache_size to 2K words from 256 to better use BSRAM | Vineet Kumar | 1 | +1 | -1 |
| 2026-08-06 17:32 | reduce pipeline critical path delay | Vineet Kumar | 7 | +229 | -194 |
| 2026-08-06 15:47 | fix pipeline by handling hazards, aligning data-memory, and registered reads | Vineet Kumar | 6 | +176 | -85 |
| 2026-08-06 13:25 | remove the unused result address from test cases | Vineet Kumar | 1 | +0 | -10 |
| 2026-08-05 09:12 | print the unmodified failed test number | Vineet Kumar | 2 | +10 | -6 |
| 2026-08-05 09:12 | test only for rv32ui right now | Vineet Kumar | 1 | +2 | -1 |
| 2026-08-04 12:42 | fix test running and remove rv64-specific tests | Vineet Kumar | 36 | +87 | -1862 |
| 2026-08-04 10:11 | vendor riscv-tests with using result address instead of zicsr | Vineet Kumar | 109 | +8497 | -17 |
| 2026-08-04 10:02 | remove github:riscv-software-src/riscv-tests submodule | Vineet Kumar | 2 | +0 | -4 |
| 2026-07-26 10:57 | pipeline register reset's pc should use BASE_ADDR const | Vineet Kumar | 1 | +3 | -2 |
| 2026-07-26 10:57 | fix wrong pipeline register being used in next_pc calculation | Vineet Kumar | 1 | +2 | -2 |
| 2026-07-26 10:56 | stop using I-cache until I fix pipelining | Vineet Kumar | 1 | +2 | -1 |
| 2026-07-26 10:56 | exit sim on a 32'b0 after any real inst | Vineet Kumar | 1 | +7 | -1 |
| 2026-07-24 08:44 | remove erroneous basic pipelining complete mention in readme | Vineet Kumar | 1 | +0 | -3 |
| 2026-07-24 08:44 | switch pipeline registers to sync reset | Vineet Kumar | 1 | +22 | -22 |
| 2026-07-24 08:17 | remove zicsr extension for now due to issues | Vineet Kumar | 7 | +11 | -432 |
| 2026-07-14 07:59 | move $display() messages to tb | Vineet Kumar | 3 | +34 | -32 |
| 2026-07-14 07:56 | properly latch the pipeline registers | Vineet Kumar | 4 | +67 | -48 |
| 2026-07-13 04:42 | remove tb prematurely exiting on ecall/ebreak | Vineet Kumar | 1 | +1 | -7 |
| 2026-07-13 04:42 | insert stall after csr regfile registered read | Vineet Kumar | 4 | +53 | -20 |
| 2026-07-12 15:40 | optimize csr address decoding from priv spec 2.1 | Vineet Kumar | 2 | +105 | -87 |
| 2026-07-12 09:35 | fix readme's claim about zicsr+mret having identical performance and usage | Vineet Kumar | 1 | +2 | -3 |
| 2026-07-12 06:46 | fix csr regfile memory inference | Vineet Kumar | 5 | +15 | -4 |
| 2026-07-11 13:00 | make unified memory have registered reads again | Vineet Kumar | 1 | +6 | -9 |
| 2026-07-11 13:00 | fix synth errors | Vineet Kumar | 2 | +12 | -5 |
| 2026-07-11 12:46 | make pnr make target depend on synth | Vineet Kumar | 1 | +1 | -1 |
| 2026-07-11 09:26 | ignore rom.txt in .gitignore | Vineet Kumar | 1 | +1 | -0 |
| 2026-07-11 09:25 | do initial pipelining | Vineet Kumar | 8 | +255 | -106 |
| 2026-07-08 09:41 | implement privileged MRET instruction | Vineet Kumar | 5 | +63 | -12 |
| 2026-07-06 12:10 | stop simulation when illegal instruction encountered | Vineet Kumar | 1 | +3 | -1 |
| 2026-07-06 12:10 | implement Zicsr | Vineet Kumar | 6 | +350 | -18 |
| 2026-07-03 15:49 | exit simulation on EXC_ILL_INST again | Vineet Kumar | 1 | +3 | -2 |
| 2026-06-18 20:58 | increase icache depth to 8K words | Vineet Kumar | 1 | +2 | -2 |
| 2026-06-12 04:42 | update readme with current progress | Vineet Kumar | 1 | +20 | -4 |
| 2026-06-12 04:41 | add librelane | Vineet Kumar | 3 | +17 | -0 |
| 2026-06-11 20:52 | make it easy to enable/disable i-cache when fetching (synth-time) | Vineet Kumar | 1 | +10 | -0 |
| 2026-06-11 01:20 | temporarily decrease cache depth to 64 words | Vineet Kumar | 1 | +2 | -1 |
| 2026-06-11 01:11 | add pnr makefile target | Vineet Kumar | 2 | +8 | -0 |
| 2026-06-11 00:45 | comment out unused async resets in hart to remove comb. rst LUTs | Vineet Kumar | 1 | +17 | -21 |
| 2026-06-11 00:44 | make fpga temp. top module and add dmem_valid output to unified_memory | Vineet Kumar | 6 | +52 | -6 |
| 2026-06-10 18:41 | check if pass and fail functions exist in test, print if not | Vineet Kumar | 1 | +3 | -1 |
| 2026-06-10 00:20 | fix shamt to be combinational assign, not initial | Vineet Kumar | 1 | +3 | -1 |
| 2026-06-09 23:01 | write data memory according to the byte location | Vineet Kumar | 1 | +24 | -8 |
| 2026-06-09 22:44 | try fixing the icache's aliasing | Vineet Kumar | 1 | +13 | -6 |
| 2026-06-09 22:44 | implement better testing infrastructure | Vineet Kumar | 7 | +85 | -313 |
| 2026-06-09 18:45 | move unified memory read to be combinational for single-cycle | Vineet Kumar | 1 | +5 | -1 |
| 2026-06-09 18:45 | change finish condition of testbench to include '0 inst | Vineet Kumar | 1 | +6 | -1 |
| 2026-06-09 04:31 | implement a sort of modified harvard arch. and icache flushing | Vineet Kumar | 7 | +129 | -44 |
| 2026-06-09 04:29 | update makefile | Vineet Kumar | 1 | +18 | -2 |
| 2026-06-08 21:45 | implement Zifencei as a nop | Vineet Kumar | 2 | +12 | -4 |
| 2026-06-08 21:40 | add rv32 toolchain to manifest.scm | Vineet Kumar | 1 | +3 | -1 |
| 2026-06-08 20:14 | increase tb imem to 1K and dmem to 4K | Vineet Kumar | 1 | +2 | -2 |
| 2026-06-08 20:14 | remove the temporary inst opcode decoding debug message | Vineet Kumar | 1 | +0 | -2 |
| 2026-06-08 19:07 | fix faulty nop detection in decoding | Vineet Kumar | 1 | +3 | -3 |
| 2026-06-08 18:53 | fix instruction decoding in decoding logic to not use initial assignment | Vineet Kumar | 1 | +13 | -6 |
| 2026-06-08 18:53 | update rom.txt to be rv32ui-p-addi and increase rom size to 1024 words | Vineet Kumar | 2 | +288 | -3 |
| 2026-06-08 18:52 | output better logging | Vineet Kumar | 2 | +17 | -5 |
| 2026-06-07 22:57 | print current cycle | Vineet Kumar | 1 | +14 | -2 |
| 2026-06-07 21:56 | add very basic testbench | Vineet Kumar | 5 | +71 | -3 |
| 2026-06-04 22:33 | replace casez with case inside | Vineet Kumar | 1 | +1 | -1 |
| 2026-06-03 20:06 | add resources and LLM disclosure to README | Vineet Kumar | 1 | +52 | -25 |
| 2026-06-03 17:19 | use gowin-specific synthesis flow | Vineet Kumar | 1 | +1 | -1 |
| 2026-06-03 02:03 | add makefile for linting and synthesis | Vineet Kumar | 2 | +24 | -0 |
| 2026-06-03 01:54 | fix synthesis issues | Vineet Kumar | 2 | +11 | -8 |
| 2026-06-02 18:58 | add .gitignore | Vineet Kumar | 1 | +2 | -0 |
| 2026-06-02 18:58 | add nop | Vineet Kumar | 1 | +10 | -1 |
| 2026-06-02 18:58 | replace writeback for loop with foreach | Vineet Kumar | 1 | +1 | -1 |
| 2026-06-02 02:57 | move remaining decode typedefs to pkg for easier debugging access later | Vineet Kumar | 2 | +89 | -89 |
| 2026-06-02 02:57 | add stubs for unused signals in hart's top-level | Vineet Kumar | 1 | +16 | -1 |
| 2026-06-02 01:19 | add writeback stage | Vineet Kumar | 2 | +29 | -1 |
| 2026-06-02 00:14 | add memory stage | Vineet Kumar | 2 | +82 | -5 |
| 2026-06-01 22:01 | add execute stage | Vineet Kumar | 4 | +123 | -22 |
| 2026-06-01 19:53 | group control signals together when decoding based on major opcode | Vineet Kumar | 1 | +55 | -193 |
| 2026-06-01 19:40 | make a package for user-defined types | Vineet Kumar | 3 | +103 | -96 |
| 2026-06-01 19:24 | add basic exception signals | Vineet Kumar | 1 | +21 | -14 |
| 2026-06-01 14:59 | l'anthorpic fishe | Vineet Kumar | 1 | +1 | -0 |
| 2026-06-01 01:48 | assign control signals for all non-SYSTEM RV32I instructions | Vineet Kumar | 1 | +246 | -2 |
| 2026-05-31 23:04 | define control signals | Vineet Kumar | 1 | +78 | -4 |
| 2026-05-31 21:26 | parse instructions into names to generate control signals | Vineet Kumar | 1 | +80 | -12 |
| 2026-05-31 20:48 | switch decoding to using major opcode enum | Vineet Kumar | 1 | +47 | -12 |
| 2026-05-31 19:58 | start working on decoding logic | Vineet Kumar | 2 | +116 | -4 |
| 2026-05-30 19:21 | fix regfile declaration to be an unpacked array | Vineet Kumar | 1 | +5 | -5 |
| 2026-05-29 06:07 | add fetching support but needs tests | Vineet Kumar | 2 | +31 | -8 |
| 2026-05-29 03:01 | add skeleton hart's top-level module with regfile | Vineet Kumar | 1 | +31 | -0 |
| 2026-05-27 20:39 | initial payload | Vineet Kumar | 2 | +254 | -0 |
