Makefile (3749B)
1 SRCDIR := rtl 2 OBJDIR := obj_dir 3 4 PKG_SRC := ${SRCDIR}/rv32g_pkg.sv 5 TB_SRC := ${SRCDIR}/tb_rv32g.sv 6 SV_SRCS := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} ${SRCDIR}/unified_memory.sv 7 TOP_SRC := ${SRCDIR}/rv32g_hart_top.sv 8 CST_SRC := ${SRCDIR}/rv32g_hart_top.cst 9 10 #NEXTPNR_DEV := GW5A-LV25MG121NES 11 NEXTPNR_DEV := GW5AST-LV138PG484AC1/I0 12 13 # tests 14 TEST_DIR := tests 15 SIM := $(OBJDIR)/Vtb_rv32g 16 CROSS_COMPILE := riscv32-unknown-elf- 17 CFLAGS := -O0 -static -fvisibility=hidden -nostdlib -nostartfiles -mabi=ilp32 18 CPPFLAGS := -I. 19 LDFLAGS := -Tlink.ld 20 21 # main 22 .PHONY: all lint synth sim_compile sim tests clean clean-tests 23 24 all: lint synth 25 26 lint: $(PKG_SRC) $(SV_SRCS) 27 verilator --lint-only --timing \ 28 +1800-2023ext+.sv \ 29 --top rv32g_hart_top \ 30 $(PKG_SRC) $(TB_SRC) $(SV_SRCS) $(TOP_SRC) 31 # --top tb_rv32g \ 32 33 synth: 34 yosys -m slang -p 'read_slang $(PKG_SRC) $(SV_SRCS) $(TOP_SRC); synth_gowin -family gw5a -top rv32g_hart_top -json design.json' 35 36 pnr: synth 37 nextpnr-himbaechel-gowin --json design.json --write design_pnr.json --freq 300 --device ${NEXTPNR_DEV} --vopt cst=${CST_SRC} 38 39 sim_compile: lint $(PKG_SRC) $(TB_SRC) $(SV_SRCS) 40 verilator --binary --exe --build --timing \ 41 --top tb_rv32g \ 42 -j 0 -o Vtb_rv32g \ 43 --trace-fst \ 44 $(PKG_SRC) $(TB_SRC) $(SV_SRCS) 45 46 sim: sim_compile 47 ./$(SIM) 48 49 # tests 50 tests-riscv-tests_compile: # crazy name 51 @cd "$(TEST_DIR)/riscv-tests" && \ 52 for i in rv32ui/*.S; do \ 53 $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32i_zifencei "$$i" -o tmp && \ 54 $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \ 55 $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \ 56 rm -f tmp; \ 57 done && \ 58 for i in rv32um/*.S; do \ 59 $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32im "$$i" -o tmp && \ 60 $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \ 61 $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \ 62 rm -f tmp; \ 63 done && \ 64 for i in rv32ua/*.S; do \ 65 $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32ia "$$i" -o tmp && \ 66 $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \ 67 $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \ 68 rm -f tmp; \ 69 done && \ 70 for i in rv32uf/*.S; do \ 71 $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32if "$$i" -o tmp && \ 72 $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \ 73 $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \ 74 rm -f tmp; \ 75 done && \ 76 for i in rv32ud/*.S; do \ 77 $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32g "$$i" -o tmp && \ 78 $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \ 79 $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \ 80 rm -f tmp; \ 81 done 82 83 tests-riscv-tests: sim_compile tests-riscv-tests_compile 84 # for i in rv32*/*.hex; do 85 @cd $(TEST_DIR)/riscv-tests && \ 86 for i in rv32ui/*.hex; do \ 87 ../../$(SIM) +rom="$$i" 2>&1 | tee "$${i%%.hex}.log" | grep -E 'pass|fail'; \ 88 done; \ 89 grep -ohE 'pass|fail' rv32*/*.log | sort | uniq -c 90 # TODO do same for gh:riscv/riscv-arch-test 91 92 # build and run all tests 93 .PHONY: tests 94 tests: tests-riscv-tests 95 @echo ${TEST_LIST} 96 @echo "All tests ran." 97 98 # clean 99 clean-tests: 100 find $(TEST_DIR) -type f -name '*.dump' -exec $(RM) {} \; 101 find $(TEST_DIR) -type f -name '*.hex' -exec $(RM) {} \; 102 find $(TEST_DIR) -type f -name '*.log' -exec $(RM) {} \; 103 find $(TEST_DIR) -type f -executable -exec $(RM) {} \; 104 105 clean: 106 rm -rf $(OBJDIR) 107 $(MAKE) clean-tests