README.org (5256B)
1 * rv32g-core 2 This aims to be a fully pipelined, synthesizable RV32G (IMAFD + Zicsr + Zifencei 3 extensions) RISC-V core written in SystemVerilog. It's designed as a passion 4 project towards making a CPU of my very own, as part of a larger goal of making 5 a portable computer with all ICs designed by me. 6 7 ** Goals 8 It will be implementing a standard-compliant RISC-V core without custom ISA 9 extensions as per the RISC-V ISA Unprivileged Architecture Manual (Version 10 20260120). The design process would be starting with a minimal single-cycle 11 RV32I core with verification through making a 5-7 pipeline to adding full 12 G-extension support. The core should be able to run at 250 MHz and have low 13 power usage. 14 15 Possibly the only thing I will include from the RISC-V ISA Privileged 16 Architecture Manual is with regards to the SYSTEM instructions so that a more 17 mainstream EEI like FreeRTOS and Linux (with enough memory) could potentially 18 run on it. I may change my mind regarding this later on. 19 20 *** ISA Support 21 - Base: RV32I (32-bit Integer Base ISA) 22 - Extensions: 23 - M (Integer Multiplication and Division) 24 - A (Atomic Instructions) 25 - F/D (Single- and Double-Precision Floating-Point) 26 - Zicsr (Control and Status Registers) 27 - Zifencei (Instruction-Fetch Fence) 28 29 *** Architecture Progress 30 1. Single-cycle RV32I (DONE) 31 2. 5-stage pipeline (DONE) 32 3. Zicsr and Zifencei (partial) 33 4. M and A extensions 34 5. 6/7-stage pipeline 35 6. Branch prediction 36 7. F and D extensions 37 8. SRAM caching (partial) 38 9. SDRAM controller 39 40 ** Target Platforms 41 - FPGA: GW5A-LV25MG121 on a Sipeed Tang Primer 25K board (Yosys, nextpnr, 42 openFPGALoader) 43 - Has 23k LUTs and a silicon fabric of 300 MHz. I'm aiming for 200 MHz at the 44 minimum. 45 - Would use the on-chip 1008Kb BSRAM and board's 2x32Mb SDRAM (Winbond 46 W9825G6KH-6) 47 - ASIC: SkyWater 130nm PDK via LibreLane Classic Flow (wraps Yosys and OpenROAD) 48 - Would start tapeout of it after all goals met and using it faces no issues 49 with FPGA 50 51 * Milestones 52 - June 11, 2026: Single-Cycle RV32I-Zifencei Completed 53 - all tests pass (except rv32ui-p-ma_data which tests misaligned accesses) 54 - no misaligned memory accesses because it's complicated to do in 55 single-cycle hardware due to needing multiple memory accesses 56 - major problem is that due to memory accesses needing to be combinational 57 (within single cycle), it forces memory and cache data to be in distributed 58 RAM (RAM16SDP4 on GoWin) and cache tags in LUTs, so synthesized memory 59 cannot be large unlike in simulation 60 - critical path dominated by this causing unoptimal routing and large number 61 of cells 62 - clock speed and LUT4s after PnR (cache_depth=64 so arc routing doesn't takes 63 hours): 64 - Without instruction memory cache: ~40.5 MHz, 15.8k LUT4 65 - With instruction memory cache: ~33.9 MHz, 24.1k LUT4 66 - July 8, 2026: Zicsr and PRIV-MRET Completed 67 - clock speed and LUT4s after PnR (cache_depth=64): 68 - With instruction memory cache: ~40.3 MHz, 154.7k LUT4, 8440 RAM16SDP4 69 - August 6, 2026: Preliminary 5-stage Pipelining Completed 70 - clock speed and LUT4s after PnR (cache_depth=8192): 71 - With I-cache: ~75.2 MHz, 3.9k LUT4, 32 RAM16SDP4, 34 BSRAM 72 - Without I-cache: ~96.7 MHz, 2.2k LUT4, 32 RAM16SDP4, 32 BSRAM 73 - August 22, 2026: Proper 5-stage Pipelining Completed 74 - clock speed and LUT4s after PnR (cache_depth=8192): 75 - With I-cache: ~100.2 MHz, 2.3k LUT4, 32 RAM16SDP4, 32 BSRAM 76 77 * Resources Used 78 - [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 79 20260120)]] 80 - used as the source of truth for what the functionality should be and what to 81 include 82 - [[https://docs.riscv.org/reference/isa/_attachments/riscv-privileged.pdf][RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Version 83 20260120)]] 84 - for finding out some of the underspecified instructions should normally do 85 like the SYSTEM ones 86 - Stuart Sutherland's [[https://sutherland-hdl.com/books_and_guides.html#RTL%20Book]["RTL Modeling with SystemVerilog For Simulation and 87 Synthesis: Using SystemVerilog for ASIC and FPGA Design"]] 88 - for properly learning SystemVerilog and its best practices since my 89 bachelor's courses did not teach Verilog well 90 - Chris Spear's and Greg Tumbush's [[https://link.springer.com/book/10.1007/978-1-4614-0715-7]["SystemVerilog for Verification: A Guide to 91 Learning the Testbench Language Features"]] 92 - for properly learning how to make a testbench 93 - David Patterson's and John Hennessy's "Computer Organization and Design: MIPS 94 Edition" 95 - this edition was used because I already owned it after taking my computer 96 architecture class (we didn't use the newer RISC-V edition) 97 - for understanding how the datapath would look like in a traditional RISC 98 architecture and how pipelining works 99 - [[https://github.com/riscv-software-src/riscv-tests][Official RISC-V Unit Tests]] 100 - would later be used in the testbenches to verify the hart 101 102 * LLM Disclosure 103 No LLM assistance was used in the writing of any of the code, so that I could 104 properly learn RTL and to take control of the actual design, not using other 105 people's work without attribution.